Synthesis techniques useful in the generation of precise microwave frequencies by Kenneth Eugene Marcotte A thesis submitted to the Graduate Faculty in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in 4 Electrical Engineering Montana State University © Copyright by Kenneth Eugene Marcotte (1972) Abstract: The general principles of direct and indirect methods of frequency synthesis are described. Signal operations of frequency translation, multiplication and division are analyzed and degradation of the input signal stability is discussed. Synthesis techniques which have application in the VHF and UHF frequency ranges under investigation are presented as follows: 1. Several broadband frequency multiplication techniques employing the Hot Carrier and Step Recovery diodes are analyzed. Graphs showing performance characteristics allow prediction for wide ranges of circuit parameters and input and output operating frequencies. 2. The analysis of a broadband frequency divider using a Step Recovery diode is presented. The divider executes subharmonic oscillations of order 1/2 and has an operational bandwidth greater than an octave in frequency. Graphs showing performance characteristics are presented. 3. A ring modulator is described using broadband transformer coupling and matched Hot Carrier diodes to perform frequency translation through 1 GHz. Experimental data presented for the VHF and lower UHF frequency range appears to confirm the analyses of the various signal operations under investigation.  SYNTHESIS TECHNIQUES USEFUL IN THE GENERATION OF PRECISE MICROWAVE FREQUENCIES "by KENNETH EUGENE MARCOTTE A thesis submitted to the Graduate Faculty in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in 4 Electrical Engineering Approved: Head9 Major Department 7CSairman9 Examining Committee i x 2 % ^ MONTANA STATE UNIVERSITY Bozeman, Montana December 1972 iii ACKNOWLEDGEMENTS To Professor Donald K. Weaver, Jr., I express my appreciation and thanks for the thoughtful suggestions and guidance in this research. I also express my thanks to the several undergraduate students at Montana State University who spent time recording and reducing data. The author wishes to express sincere appreciation to all members of his committee for their encouragement and helpful criticism in the preparation of this work. The research reported in this writing was sponsored by NASA and the Electrical Engineering Department. Thanks are extended to all who made the financial support possible. Thanks are also extended to the John Fluke Manufacturing Company, Seattle, Washington, for the financial support used to purchase semiconductor devices. Finally, but by no means least in importance, the author expresses his appreciation to his wife, Colleen, for her unending understanding and intensive efforts in typing and retyping the material for publication. TABLE OF CONTENTS Page 1.0 STATEMENT OF THE P R O B L E M ................................. I 2.0 FREQUENCY SYNTHESIS . . . . . . ........................... U 2.1 DIRECT FREQUENCY SYNTHESIS................ 5 2.2 INDIRECT FREQUENCY SYNTHESIS. . ........... •. . . 8 2.3. SYNTHESIZER PERFORMANCE SPECIFICATIONS ........... 11 2.1* SUMMARY .... ....................................... .. 11* 3.0 SIGNAL REPRESENTATIONS AND OPERATIONS APPLICABLE TO FREQUENCY SYNTHESIS...................... ............. 15 3.1 SIGNAL REPRESENTATION................■............ .. 15 3.2 FREQUENCY TRANSLATION.......................... IT 3.2.1 GENERAL TRANSLATION . . . . . . . . . . . . 17 3.2.2 GENERAL MIXER......................... , _ . . . . 19 3.2.3 SINGLE DIODE M I X E R .................... -. . . 20 3.2.U BALANCED MIXERS............................... 23 3.3 FREQUENCY MULTIPLICATION ......... 29 3.1* FREQUENCY DIVISION .... ................... 33 I*.O ANALYSIS OF TECHNIQUES INVESTIGATED . . . . . . . . . . 36 I*.I SEMICONDUCTOR DEVICE CHARACTERIZATION . . . . . . . 37 I*.2 MULTIPLICATION . . . ............................... . 39 I*.2.1 RECTIFIER DIODE HARMONIC GENERATORS . . . . Ul ' U.2.2 BROADBAND NONLINEAR CAPACITOR HARMONIC GENERATOR. . . . . . .............. . . . . U6 iv Vk.2.3 BROADBAND STEP RECOVERY DIODE HARMONIC GENERATOR........... ' ......................... 51 k.2.b STEP RECOVERY DIODE HARMONIC GENERATOR WITH RESONANT LOAD . ................ .. 68 4.3 D I V I S I O N ............. 82 4.3.1 BROADBAND STEP RECOVERY DIODE FREQUENCY DIVIDER........................... . 84 /4.4 TRANSLATION........................ 97 4.4.1 BROADBAND DOUBLE BALANCED MODULATOR......... 97 5.0 EXPERIMENTAL R E S U L T S .................... .. . •........... 99 5.1 M U L T I P L I C A T I O N ............. .. I IOO 5.1.1 RECTIFIER DIODE HARMONIC GENERATOR ......... 101 5.1.2 BROADBAND SRD GENERATORS.................. . H O 5.1.3 SRD RESONANT LOAD HARMONIC GENERATORS. . . . 118 5.2 DIVISION ......................................... . 123 5.3 TRANSLATION . ................ •.......... .. . ........ 139 6.0 SUMMARY AND CONCLUSIONS ............................... . l48 6.1 SUMMARY OF RESULTS........... l48 6.2 SUGGESTIONS FOR FURTHER RESEARCH. . . . . . . . . . . 150 APPENDIX A DERIVATION OF SHORT-TERM FREQUENCY STABILITY . . . . . . . . . . . . . . . . . . . . 153 APPENDIX B NONLINEAR DEVICE ANALYSIS ......... . . . . . . . 158 APPENDIX C CALCULATION OF THE HARMONIC SPECTRUM • • OF A .CLIPPED SINE W A V E .........l6l APPENDIX D .NONLINEAR CAPACITOR ANALYSIS . . . . . . . . . . . . 163 vi . APPENDIX E STEP RECOVERY DIODE ANALYSIS .................... 167 APPENDIX F STEP RECOVERY DIODE FREQUENCY DIVIDER ANALYSIS . .................. ■............ 177 ' APPENDIX G BALANCED MODULATOR ANALYSIS . .................. . 183 APPENDIX H DIGITAL COMPUTER PROGRAM LISTINGS ............... 185 LITERATURE CITED ............... . . . . . . . . . . . . . . 198 'LIST OF TABLES Table Page U-I R M G E OF ........................................... 72 4- 2 OVERALL CONVERSION EFFICIENCY DEGRADATION . . . . . 82 5- 1 DIODE P A R A M E T E R S ....... - .................... .. . 101 5-2 L M D C VALUES OF FREQUENCY DIVIDERS................ 123 vii viii LIST OF FIGURES 2-1 BLOCK DIAGRAM OF DIRECT FREQUENCY SYNTHESIS . . . 6 2-2 GENERAL BLOCK DIAGRAM FOR DIRECT FREQUENCY-SINGLE SOURCE SYNTHESIZERS ............. 7 2-3 ' AUTOMATIC PHASE CONTROL SYSTEM BLOCK DIAGRAM . . . 9 2-1+ DIGITAL FREQUENCY SYNTHESIS BLOCK DIAGRAM.... IO 2- 5 OUTPUT SPECTRUM OF A FREQUENCY STANDARD. . . . . . 12 3- 1 FREQUENCY TRANSLATION ............................. 18 3-2 CONVENTIONAL M I X E R ................................. - 23 3-3 HALF LATTICE BALANCED M O D U L A T O R ............. 2k 3-1+ RING MODULATOR.......................................... 26 3-5 IDEAL FREQUENCY MULTIPLIER................... 29 3- 6 IDEAL FREQUENCY DIVIDER........................ 34 4- 1 IDEAL NONLINEAR RESISTOR CHARACTERISTICS .......... 38 4-2 IDEAL NONLINEAR CAPACITOR CHARACTERISTICS . . . . 38 4-3 RECTIFIER GENERATOR EQUIVALENT CIRCUITS...... 42 4-4 CLIPPED SINE WAVE OUTPUT SPECTRUM n EVEN . . . . . 43 4-5 CLIPPED SINE WAVE OUTPUT SPECTRUM n ODD........... 44 4-6 MAXIMUM SPECTRUM AMPLITUDE-CLIPPED SINE WAVE GENERATOR...................................... 45 4-7 . BROADBAND HARMONIC GENERATOR EQUIVALENT CIRCUIT. . 47 4-8 N-C HARMONIC SPECTRUM n EVEN . ..................... 48 4-9 N-C HARMONIC SPECTRUM n O D D ....................... 4g Figure ■ Fage ZX Figure , ■ Page Il--IO MINIMUM CONVERSION LOSS FOR N-C GENERATOR ........................................ 50 U - H SRD BROADBAND MULTIPLIER EQUIVALENT CIRCUIT AND CURRENT N A V E F O R M .................................. 52 4-12 0 AND n EVEN ..........................69 4-27 CONVERSION LOSS VS * n O D D ........................... 70 ' 4-28 RANGE OF cj>........... ; ......................... .. '. 71 4-29 EQUIVALENT CIRCUIT OF HARMONIC GENERATOR WITH A RESONANT LOAD . .............................. 73 4-30 CONVERSION LOSS Q1 = .1 to 1.0 R-L SERIES C I R C U I T .............. ........................... .. 76 4-31 CONVERSION LOSS Q = 1.6 to 80 R-L SERIES CIRCUIT . . . . T . * ............................. 77 4-32 0 AND CONDUCTION CHARACTERISTICS.................... 78 4-33 HARMONIC POWER LEVEL RLC PARALLEL CIRCUIT.............79 Figure Page 4-34 MINIMUM CONVERSION LOSS AS A FUNCTION OF Q . . . . '80 4-35 MINIMUM CONVERSION LOSS AS A FUNCTION OF Q /n. . . 8l 4-36 BROADBAND DIVIDER EQUIVALENT CIRCUIT .............. 85 4-37 DIVIDER EQUIVALENT CIRCUIT USED FOR ANALOG SIMULATION...................................... . 87 I 4-38 DIVIDER WAVEFORMS 500 MHz O P E R A T I O N ............. 88 4-39 .DIVIDER WAVEFORMS 500 MHz POWER-FREQUENCY CHARACTERISTICS . ..................................... 89 4-40 DIVIDER WAVEFORMS 750 MHz O P E R A T I O N .................90 4-4l DIVIDER. WAVEFORMS -750 MHz POWER-FREQUENCY CHARACTERISTICS . . . . . . . ................•. 91 4-42 DIVIDER WAVEFORMS 1000 MHz OPERATION.............. 92 UFUT A l n l p f q S g n f D u q e 4 -1000 e v : 9 u S f q FD q f j 7 f x r 2 CHARACTERISTICS . ..................................... 93 4-44 DIVIDER FREQUENCY CHARACTERISTICS..................... 94 4-45 DIVIDER OPERATIONAL POWER LEVEL.................... . 9 6 5-1 RECTIFIER DIODE HARMONIC GENERATOR CIRCUITS. . . .. 102 5-2 CLIPPED SINE WAVE HARMONIC GENERATOR OUTPUT. . . . 103 Figure 1 Page 5-3 CLIPPED SIEE FAVE HARMONIC GENERATOR O U T P U T ................. ............................ IOlt 5-U- MEASUREMENT D I A G R A M ................................ 105 5-5 FULL WAVE HARMONIC GENERATOR OUTPUT............... 107 5-6 FULL WAVE HARMONIC GENERATOR OUTPUT. 108 5-7 INPUT LEVEL VARIATION - FULL WAVE GENERATOR. . .. . 109 5-8 CORRECTION CURVES FOR SRD MULTIPLIERS.............. Ill 5-9 BROADBAND SRD GENERATOR CIRCUIT............. .. . . 112 5-10 BROADBAND SRD GENERATOR OUTPUT hp 0 1 0 2 .......... 113 5-11 BROADBAND SRD GENERATOR OUTPUT hp 0103 . . . . . . lilt 5-12 BROADBAND SRD GENERATOR OUTPUT hp 0 1 1 2 ...........115 5-13 . BROADBAND- SRD GENERATOR OUTPUT hp 0 1 1 4 .......... Il6 5-14 BROADBAND SRD GENERATOR OUTPUT hp 0 1 5 1 ...........117 5-15 RESONANT LOAD SRD HARMONIC GENERATOR CIRCUIT . . . 119 5-16 SRD GENERATOR OUTPUT WITH TRANSFORMER INPUT AND RESONANT LOAD,.......................... 120 5-17 SRD GENERATOR OUTPUT VfITH TUNED INPUT AND RESONANT LOAD . . . .................. .............122 5-18 DRIVE LEVEL 100-200 MHz DIVIDER........... 125 5-19 EFFECT OF IMPEDANCE VARIATION 100-200 MHz D I V I S I O N ........... v ................. . 126 5-20 DRIVE LEVEL 200-400 MHz DIVIDER............. 127 5-21 ’ EFFECT OF IMPEDANCE VARIATION 200-400 MHz' D I V I D E R ............. ...........C ................. 128 xi xii 5-22 DRIVE LEVEL 350-700. MHz DIVIDER.................... 129 5-23 EFFECT OF IMPEDANCE VARIATION 350-700 MHz DIVIDER................................... 130 5-24 DRIVE LEVEL 500-1000 MHz DIVIDER .................. 131 5-25 EFFECT OF IMPEDANCE VARIATION 500-1000 MHz DIVIDER . .• . . . '................132 5-26 OUTPUT SPECTRUM- AND WAVEFORM 500-1000 MHz DIVIDER f . = 520 M H z ...................... . . . 134in 5-27 OUTPUT SPECTRUM AND WAVEFORM 500-1000 MHz DIVIDER f . = 750 M H z .............................. 135in 5-28 OUTPUT SPECTRUM AND WAVEFORM 500-1000 MHz' DIVIDER f . = 1000 M H z ...........................■ . 136in 5-29 OUTPUT SPECTRUM AND WAVEFORM 200-400 MHz DIVIDER f. = 300 MHz . . .......................•. 137in 5-30 OUTPUT SPECTRUM AND WAVEFORM 100-200 MHz DIVIDER f . = 100 M H z ........................ 138in 5-31 RING MODULATOR C I R C U I T ..............................l40 5-32 FULL LATTICE MODULATOR CONVERSION L O S S ............. l4l 5-33 FULL LATTICE MODULATOR CONVERSION L O S S ............. 142 5-34 FULL LATTICE CARRIER REJECTION .... ................ l44 5-35 EFFECT OF FULL LATTICE INPUT IMPEDANCE V A R I A T I O N ............................................145 5-36 BALANCED TRANSFORMER' DATA.......... .............. l46 C-I HARMONIC GENERATOR EQUIVALENT CIRCUIT............ l6l C-2 OUTPUT WAVEFORM FOR HARMONIC ANALYSIS QF THE CLIPPED SINE WAVE ............... l6l Figure Page nI xiii Figure Page D-I NONLINEAR CAPACITOR EQUIVALENT CIRCUIT . . . . . . 163 D-2 OUTPUT WAVEFORM FOR NONLINEAR CAPACITOR A N A L Y S I S ......................................' . D-3 cj. AND 6 FOR NONLINEAR CAPACITOR ANALYSIS . . . . . 165 E-I STEP RECOVERY DIODE GENERATOR EQUIVALENT CIRCUIT ........................................ E-2 OUTPUT WAVEFORM FOR STEP RECOVERY DIODE CIRCUIT ................................. E-3 HARMONIC GENERATOR WITH RESONANT LOAD EQUIVALENT CIRCUIT ............................. F-I SERIES STEP RECOVERY DIODE AND RESISTANCE EQUIVALENT CIRCUIT ....................... . • ITT F-2 %^WbB A"PzRPM W, GtKy RKbKW1KR. A"WAK "V GKR"KG J"tO RY G"Mh^Pt"WV.................. F-3 SIMULATED DIODE CHARACTERISTICS............. . . IT 9 F-k SRD DIVIDER EQUIVALENT CIRCUIT FOR SIMULATION. . . 180 F-5 BLOCK DIAGRAM OF BROADBAND DIVIDER -SIMULATION. . . 182 G-I DOUBLE BALANCED RING MODULATOR ............... G-2 SWITCHING FUNCTION f(t) ...................... xiv ABSTRACT The general principles of direct and indirect methods of ■ frequency synthesis are described. Signal operations of frequency translation, multiplication and division are analyzed and degradation of the input signal stability is discussed. Synthesis techniques which have application in the VHF and UHF frequency ranges under investigation are presented as follows: 1. Several broadband frequency multiplication techniques employing • the Hot Carrier and Step Recovery diodes are analyzed. Graphs showing performance characteristics allow prediction for wide ranges of circuit parameters and input and output operating frequencies. 2. The analysis of a broadband frequency divider using a Step Recovery diode is presented. The divider executes subharmonic oscillations of order 1/2 and has an operational bandwidth greater than an octave in frequency. Graphs showing performance characteristics are presented. 3. A ring modulator is described using broadband transformer coupling and matched Hot Carrier diodes to perform frequency translation through I GHz. Experimental data presented for the VHF and lower UHF frequency range appears to confirm the analyses of the various signal opera­ tions under investigation. 1.0 STATEMENT OE THE PROBLEM. Frequency synthesis is the generation of sinusoidal rf signals of a desired frequency from a frequency standard in such a manner that the accuracy and stability of the derived frequency is not seriously degraded from that of the standard. Modern communication systems and precision laboratory measurement techniques in many different fields require signal sources which possess this frequency precision and stability. Electronic circuits and system techniques for use in solving the specific frequency synthesis requirement are fairly well known for the frequency range of a few cycles per second to several hundred megacycles per second'[1-7]. This is not the case for the lower UHF and microwave frequencies. This study treats several syn­ thesis techniques which have direct application in the VHF, UHF, and microwave frequency ranges. This thesis is divided into six chapters. The statement of the problem and a discussion of techniques to be investigated for application in frequency synthesis systems are presented in Chapter I. The system concept of a frequency synthesizer is presented in Chapter 2. The significant differences in the overall system opera­ tion are discussed with the aid of several block diagrams of typical direct and indirect synthesis methods. In Chapter 3 signal operations, which are used in either the direct or indirect synthesis methods, are analyzed. These operations are frequency translation, multiplication and division. The purpose- 2of this chapter is to investigate the input signal stability degrad­ ation in' the output signals with reference to input as the signal operations are performed. The basic operating principles and analysis of techniques of performing a desired signal operation are presented in Chapter U. Many authors have described the various performance characteristics of- several of the techniques under investigation, but no one of these has treated the data presentation in a manner with sufficient depth for the general design situation. In these cases theoretical computations have been carried out and the results presented in a manner which is felt-presents' a much broader scope. These presenta­ tions allow performance prediction for wide ranges for variation of circuit parameters, of operating characteristics and of input or output operating frequencies. The analysis presented formulates the basic operational limitations regarding the signal operation being considered, and gives the basis by which experimental results of implemented operation may be compared. In Chapter 5 the design, implementation and testing of the techniques analyzed in Chapter U are carried out to determine the performance capabilities of the practical realization. In Chapter 6 the summary and conclusions .are presented. Several specific application of the investigated signal operation techniques are discussed. Suggestions for further research investigations are also presented. ,2.0 FREQUENCY SYNTHESIS When crowding of the frequency spectrum was not a problem and frequency inaccuracies could be tolerated, the tunable L-C oscillator S was a practical means of providing the required channel frequencies for various multi-channel equipment. Crowding of the spectrum required closer channel spacing and increased frequency accuracy. The crystal oscillator was used to satisfy this required increased frequency accuracy. The multiple-crystal synthesizer was developed to satisfy the requirements of multi-channel equipment. The single crystal., frequency synthesizer was proposed to fulfill the accuracy and stability requirement in equipment covering a very large number of communication channels. The single crystal frequency synthesizer retains the properties of the multiple crystal synthesizer and at the same time eliminates the problem of maintaining a large number of crystals to the same accuracy. The accuracy and stability of the output signal are essentially equal to that of the reference oscillator. Present day frequency synthesizers, regardless of the synthesis scheme used, have the common objective of referencing all generated frequencies to a single standard frequency. This single standard frequency is generated by an extremely accurate and stable oscillator. The required output frequencies are obtained in some synthesis procedure by direct multiplication and ,division of the standard frequency, which are combined by the operation of either addition or 5subtraction to give the derived output frequency. In other schemes, the final output frequency is compared directly or divided down to a frequency which can be compared with the standard frequency. The comparator output furnishes the control signal for locking the output signal to the standard. Synthesizers can be divided into two main categories. These are termed direct and indirect. Mixing of a set of frequencies derived directly from the standard to obtain the final specific output frequency is defined, as -direct synthesis. Methods which ultimately control the output of a phase-locked oscillator are defined as indirect synthesis. The common characteristic regardless of the synthesis method employed is to generate a desired frequency from a frequency standard in such a manner that the stability and accuracy of the derived frequency is not seriously degraded from that of the standard. The multiplicity of output signals available are all harmonically related to a specific subharmonic of the standard oscillator. ' 2.1 DIRECT FREQUENCY SYNTHESIS. For frequency generating systems that are classed as direct synthesis the general principles of operation can be illustrated as in Fig. 2-1. From this block diagram it is clear that the output frequency is related to a subharmonic of the reference oscillator. [ 6The selection of positive integers a and b will determine the sub harmonic spacing between available output frequencies. multiplier divider mixer Reference Oscillator Fig. 2-1. BLOCK DIAGRAM OF DIRECT FREQUENCY SYNTHESIS. P Io 1 7In the actual system realization of a synthesizer using this method to obtain many possible output frequencies, a highly stable reference oscillator with multiples and sub-multiples are mixed in elaborate ways to produce the desired outputs. A more general block diagram, which indicates the complexity that may be involved in generating a set of output frequencies for a given application, is illustrated in Fig. 2-2. output Cs) multipliers dividers multipliers selectivity switching mixers Fig. 2-2. GENERAL BLOCK DIAGRAM FOR DIRECT FREQUENCY— SINGLE SOURCE SYNTHESIZERS. 8The synthesizer of least system complexity would consist of multipliers and dividers directly connected to the reference oscilla­ tor and their outputs used to generate the desired output frequencies. The next level of system complexity would he several parallel multiplier-divider combinations to generate the desired outputs. The complexity can be continued on to the multipliers and dividers that are not directly connected to the reference oscillator. The majority of synthesizer equipments that have been built fall under this category. These systems typically provide I to 50 million frequencies that are manually selectable. 2.2 IEDIBECT FEEQUEECY SYNTHESIS. For frequency generating systems that are classed as indirect synthesis, a controlled oscillator feeds the output terminals of the synthesizer directly. The frequency of the output oscillator is continuously monitored and compared to a reference frequency, and automatic adjustment of the oscillator frequency is made to maintain its output at precisely the desired frequency. . As in the direct synthesis class, this discussion cannot include all the many types of synthesizers that have been developed in the indirect synthesis category. Two examples have been selected that include a wide cross-section of the systems in this class. The automatic phase control (APC) method of frequency synthesis1 9is presented in Fig. 2-3. This system is an electronic servo that does not'permit a steady-state frequency error to he developed between the reference frequency and the voltage controlled oscilla­ tor (VCO). Synchronized Output Control Voltage Phase Comparator and. Control Mixer Generator Harmonic Sub- Synthesizer and Frequency Standard' |nfl ± f ol Fig. 2-3. AUTOMATIC PHASE CONTROL SYSTEM BLOCK DIAGRAM. 10 The VCO output is mixed with a harmonic of the sub-synthesizer output This produces an intermediate frequency signal f ^ which is compared in the phase comparator with f ^ from the sub­ synthesizer. The comparator output is a voltage proportional to the phase error of the converted f ^ signal to the synthesizer signal. The comparator output is passed to the control circuitry of the VCO. The APC system holds the VCO on frequency by varying the control voltage so that the two f ^ signal frequencies are identical but, in general, differing in phase. This overall operation provides a frequency lock for f = |nf^ ± f^f |. Figure 2-4 illustrates an example of digital method of indirect frequency synthesis. The output of the VCO is divided by n and fed to the phase comparator. Synchronized Output Voltage Control Divider Phase Comparator Divider Frequency Fig. 2-4. DIGITAL FREQUENCY SYNTHESIS BLOCK DIAGRAM. 11 The comparator has the divided reference frequency, f , as the other input. The output of the phase comparator provides the VCO correction voltage if the two inputs are not identical in frequency. Therefore, the frequency of the VCO is automatically phase-locked to the reference standard. 2.3 SYNTHESIZER PERFORMANCE SPECIFICATIONS. In general, the system application determines the performance and configuration of the synthesizer. The specific application will dictate several or all of the following performance specifications: 1 ) frequency coverage and resolution 2) method of frequency selection 3) speed of switching to desired output frequency 4) accuracy and stability 5) spectral purity. The rf tuning range for a specified application (or equipment) in which the synthesizer is to be incorporated.will in general set the frequency coverage needed. The system channel capability will determine the number of incremental frequencies required for communications applications. Spectral purity is one of the more critical performance factors of a synthesizer. Complete spectral purity implies the absence of noise and spurious frequencies. In general the reference frequency 12 standard used to drive a synthesizer will be of resenable quality and possess an output signal power spectrum as shown in Fig. 2-5- Fig- 2-5. OUTPUT SPECTRUM OF A FREQUENCY STANDARD. The output signal of the frequency standard is specified by the harmonic distortion present9 the non-harmonic related outputs, and the signal-to-noise ratio for a specific output signal bandwidth. Each, of the quantities are specified in db. The db (decibel) measure is defined as where, for the specification of a frequency standard, y j is the power at the output frequency f . For the harmonic distortion specifi- 0 fo H y j number of db = -10 log i (2-1) cation, P^ is the power at each of the harmonics of fQ For the 13 non-harmonic components, is the power at each of the spurious frequencies. For the signal-to-noise ratio is the total power associated with the specified output signal bandwidth. A high order of spectral purity existing in the synthesizer output requires that noise and spurious frequency generation be kept to a minimum throughout the entire synthesis process. The spurious frequencies appearing in the synthesizer output are the result of either the filters used within the synthesizer presenting a finite attenuation (rather than infinite) to undesired frequency components or improper shielding of the various subsystems. In some cases the spurious outputs may be a combination of both the filtering and shielding problems. Spurious frequency generation coupled with a find incremental frequency resolution capability requires much greater system complexity. Direct frequency synthesizers have been constructed which maintain the spurious component level at 90-100 db below the desired output signal levels. Indirect synthesizers, using filter time-constants up to I second in the control loop, have been able to obtain spurious levels.greater than 100 db below the output level. The stability of the synthesized outputs are dependent on' both spurious levels and the frequency.resolution. In applications requiring fast switching between selected output frequencies, the design dictated is usually the direct method. Ih The required control loop filters in the indirect method limit their speed of response due to the "bandwidth of the filter used. 2.4 SUMMARY An attempt has been made to show that frequency synthesizer designs evolve from a few basic signal operations. The signal operations are frequency translation, frequency multiplication and frequency division. The grouping of these signal operations may be performed in a wide variety of combinations depending upon the specific system requirement. By skillful choice of operations, systems may be designed for a given application with an accuracy limited only by the primary reference oscillator. 3.0 S I G M L REPRESENTATIONS AND OPERATIONS APPLICABLE TO FREQUENCY SYNTHESIS. ' The "basic signal operations that must be combined to describe a specific frequency synthesizer of the two broad classes discussed in Chapter II are frequency translation, frequency multiplication and frequency division. In all these operations the prime concern is minimum degradation of the initial standard short-term stability while performing the desired operation. These signal operations are defined and their theoretical performance criteria set down. This then will form the basis to which actual circuit performance can be compared. 3.1 SIGNAL REPRESENTATION The signal and noise which the basic standard delivers at the output terminals is the input signal for the various signal opera­ tions considered. This signal is assumed to have a large signal- to-noise ratio along with a very narrow output signal bandwidth. It is assumed that the standard has been in operation for a sufficient length of time such that the start-up transients of the standard can be neglected. Also, the long-term effects of frequency drift in the standard output due to component drifts from aging or temperature fluctuations will not be considered in this analysis. These long­ term effects can be eliminated by appropriate control of the ■ standard. As in any system there exist possible transient responses i6 along- with the normal steady-state response for the signal operations being analyzed. The analysis that follows is concerned only with the steady-state response. For the stated assumptions the signal being generated by the standard can be expressed as s(t) = A cos w^t. . (3-1) and the noise being considered expressed as v (t) = v (t) cos to t + v . (t) sin w t. (3-2) n c o s o A = fixed amplitude kuj = standard output frequency v (t) and v (t) are both narrow-band random processes which are C S slowly varying functions compared to the individual cycles of s(t). A detailed discussion leading to equation (3-2) may be found in reference [8]. The result of adding signal and noise to obtain the output “signal delivered by the standard is V1 Ct) = s(t) + vn (t) (3-3) Substituting (3-l) and (3-2) into (3-3) yields (t) = (A + v (t)) cos to t + v (t) sin w t I C O S ' O = B(t) cos (wQt + (t)). (3-4) 17 where B(t) = \J(A + Tc Ct))2 + "VgCt)2 (3-5). and tan *(t) = STTET ’ C (3-6) For large signal-to-noise ratios 4>(t) = A-1Tg (t) (3-7) Equation (3-*0 to (3-7) specify the input signal to he used in the analysis of the signal operations presented in this Chapter. A complete model of the standard, setting down the mechanisms by which it generates this output signal, has not been described. The signal and noise that it delivers to the next element of the system is the oscillator feature of interest. 3.2 FREQUENCY TRANSLATION. Frequency translation has been used for many years, but the general problem of spurious frequency generation has often been treated lightly or ignored. In this section some of the general properties of frequency translation including the generation and suppression of spurious frequencies is discussed. X 3.2.1. GENERAL TRANSLATION Mixers with filtering perform the function of frequency trans­ lation in a signal chain. Mixing is essentially a modulation 18 in which one signal is modulated by another signal producing the lower and upper side frequency components. Mixing action is achieved, by means of a non-linear device and thus many frequency components may be present in the output of the mixer circuit. The operating parameters of the mixer stage will determine the ratio of the desired output(s) power level to the undesired outputs. Frequency translation is in general accomplished by multiplying the signal to be translated by a sinusoidal signal of appropriate frequency to provide the desired translation. For the ideal case, consider Vg (t) in Fig. 3-1 to be given by V g (t) = cos Wgt. (3-8) Then the output v (t) is expressed as y (t ) = v ^ (t) cos Wgt. (3-9) .$5* Desired Sum or Difference Frequency t Vg(t) : : •/ Fig. 3-1. FREQUENCY TRANSLATION. v1 (t). Mi XAr■ Filter V (t) .O 19 Fourier analysis shows that this, process translates the input frequency co^ or an input frequency spectrum "by an amount ± For a single input frequency, , the frequencies existing in the output are given by 0) = OL ± urn. ' (3-10)o ± id The desired sum or difference frequency is selected by filtering. 3.2.2 GENERAL MIXER As previously stated, mixing action is fundamental to the process, of frequency translation and is accomplished by use of a nonlinear device; as a result, modulation products in the output will exist and many frequencies other than ± cOg along with possible addi­ tional spurious responses at UJq . Considering a general nonlinear mixer, the output V Q (t) may be expressed as 1 j wt) = I I Bmn cos (mc^t ± nwgt + .. (3-11) m=o n=o where "■ . a = constant mn <{> = constant phase shift mn Spurious responses are generally produced with signals existing at ■ undesired frequencies which satisfy the following condition fo = ImfI - nf2 l (3-12) where = signal frequency fg = translation frequency f = desired output frequency m and n are integers >_ I. The choice of frequencies which are to he used in the trans­ lation scheme depend on several.factors. This dependence in all cases relies on how well the extraneous signal can he rejected in the output of the mixer. Several means are available to aid in accomplishing the required rejection such as narrow-hand filters, frequency spacing, and an effective cancellations of many components hy balancing techniques. In the desired translation case the frequency of translation and' the sets of harmonic sum and difference components do not fall within the output bandwidth of the mixer. In these cases the required extraneous signal rejection is provided hy the filter response in the mixer output. In the cases where ■ the translation signal frequency falls in the output signal band­ width, balancing is required to eliminate these components. The next two sections describe unbalanced and balanced mixers. 3.2.3. SINGLE DIODE MIXER The single diode mixer will be presented in,terms of solid state diode mixers in that the conversion conductance analysis 21 applies directly. The analysis can be extended to the transistor mixer by considering a diode mixer followed by a transistor ampli­ fier. Then the conversion gain is the sum of the diode conversion loss at the linear signal frequency.and the transistor gain at the desired output frequency. The high conductance of a diode in the forward direction and very low conductance in the reverse direction provides the necessary non-linearity for mixing. The dc voltage-current characteristics of the diode is expressed as M t ) = Io [e-WtHiq) „!] = I akv(tjk (3-13) k=o where 1j is the dc bias voltage, a^ . is related to the diode conduc­ tance, and v(t) is the total instantaneous ac voltage across the junction. Therefore, no diode mixer is truly piecewise linear nor truly square law in its operation. The commonly used diode is an exponential law mixer. The exponential expression expanded as a Taylor series yields 2 "3 i(t) = aQ + a^v(t) + a^v (t) + a^w (t) + ... - (3-1*0 The output voltage for a conventional mixer, Fig. 3-2, is equal to the diode current times the load, resistance. The voltage, v(t), is the sum of the translating and signal voltages. 22 V1 Ct) and VgCt), Applying v^(t) = sin uM: and Tg (t) = A^ sin t to the mixer, 2* the current expression for v(t) = v^(t) + V0 (t) becomes i ( t ) = aQ + aI (A1 cos mIt + A 2 cos > + a2 (A1 cos 3- + A 2 cos +3Gre + a3 (A 1 cos U) t + A 2 cos > = aQ + a1 A1 cos w1t + U1 Ag cos w^t + a2Al + a2A2 + a2Al cos 2w1t ' a2A2 ^ + — -— cos 2(0gt + a2A1 Ag cos (^1 + u)g)t + agA1 Ag cos (O)1 - u)g)t - ■ + ... (3-15). If equation (3-lU) contains high order terms then the diode current expression (3—15) will have components associated with the harmonic sum and difference frequencies. In the output of the mixer for the case a^ ^ o for n > 2, the frequency components present are ^1 ,"Wg, u^ ± 'u)g, mu^, nWg, mu)1 ± nuig (m and n are integers). 23 The signal-to-noise ratio of this mixer with an ideal trans­ lating signal and coefficients higher than a^ being zero will be D Fig. 3-2. CONVENTIONAL MIXER. that of the signal input. However, if even ordered coefficients greater than a^ are not zero then the output signal-to-noise ratio will be degraded since these products fall in the desired output bandwidth and therefore cannot be removed by filtering. 3.2.4 BALANCED MIXERS The single diode mixer discussed generates a large number of spurious products. Suppression of the signal and translation frequencies along with some of the harmonic differences generated is desired. Two types of balanced mixers, generally called full lattice and half lattice, are commonly employed to meet these requirements. The half lattice modulator allows suppression of only 'j one of the injected signals. The full lattice or ring modulator ;| 2k allows suppression of Poth injected signals and their harmonics. However, some harmonic sum and difference components still remain. The half lattice modulator can he represented as shown in Tig. 3-3. Pig. 3-3 . HALF LATTICE BALANCED MODULATOR. Assuming balanced diodes and transformers the output currents i^(t) and ig(t) are expressed as 2 3 , _ i_ = a + a, v + a0 v + a_ v + ... I o l c; J i2 = aQ + a1 v + a2 v2 + a3 v3 + ... , (.3-16) *1 + Vg "V1 + v 2 * % where 25 These voltages and currents are all functions of time as was the case in the single diode analysis. The notation has "been changed merely for simplicity. The modulator output across is given "by vo Cii - i2 ) Rk d (2aL vL + Iia2 V ^ v 2 + v ^ 2 3+ 6a_ V1 v2 + Ba^ V1 v2 + Ba^ V1 v2 + .) (3-17) As "before, if we consider only coefficients aQ , U1 , and a2 , we obtain the desired translation, w + Wg, with no degradation in the signal-to-noise ratio at the output. The even harmonics of ^1 and all harmonics of w2 have been cancelled out. For the general case, a^ ^ o for n > 2, the frequency components present are W1 , W1 i Wg, nw1 , mWg ± Uw1 (m an integer and n an odd integer). As in the single diode case, the signal-to-noise ratio will be degraded if the even ordered coefficients greater than a2 are not zero. The double balanced ring or full lattice modulator is shown in Fig. 3-4. Using the same analysis as used for the half lattice modulator and balanced transformers and diodes the load currents are those of the previous modulator plus two additional currents associated with the reversed polarity diodes and D^. The load currents due to the addition of these diodes are - 26 2 3 U1 = a - a„ V + a_ V - a„ V + aU V I . O I 2 2 3 3 UI = a — a_, V + a_ V - a„ V + % V2 O I 2 3 (3-18) Fig. 3-U„ RIUG MODULATOR. The negative signs are the result of reversing the polarity and cross-connection of the additional diodes. These current equations are obtained by substituting in equation (3-16) -v and -T for v and v respectively. The output voltage associated with these currents is 27 ( i i - i P RL RL + ^ 2^ 2 - - Sa3V1V32 + Sa1^v13V2 + Sa1^v1V23 + ... ] (3-19) The output voltage for the ring modulator is obtained by adding equations (3-17) and (3-19) which yields O Q xi v VFg [Sa5V1V2 + ISaljV1 Vg + ISa^v1 V2 + ...] (3-20) Considering coefficients aQ , B1 , and a2 , we obtain the desired translation ^1 ± Wg with the cancellation of the two input signal frequency components. For the general case, a^ ^ 0 for n > 2, the components present in the modulator output are mw2 ± nu^ (m and n odd integers). A comparison of the spurious products in the output of the several mixers discussed clearly points out the advantage of the ring modulator. The statement was made regarding the various mixer circuit configuration considered as to a reduction of the input signal-to- noise ratio in the mixer output if the even order coefficients greater than a2 were not zero. This can be easily checked by considering a higher order expansion and using equation (3-4) as the expression for the input signal and assuming a noise-free, sinusoidal translation signal at'frequency fg. It will be found that the noise level is increased for the condition of a higher order transfer function than a2 « In Appendix A-the short-term frequency stability of a signal is 28 related to the existing signal-to-noise ratio. This relationship provides a means for determining the effects on the stability for a given decrease in the mixer output signal-to-noise ratio. The common definition of short-term stability (for measurement interval T ) is used in the derivation of Appendix A. Short-term stability is the ratio of the rms frequency deviation in the measurement time to the nominal frequency. The relationship between the fractional frequency stability and the signal-to-noise ratio is given by ' W1 '■ I il/S (SWR)1T (SER)2T2 (3-21) where Wo = Midband angular frequency (SWR)1 = Signal-to-noise associated with memory type (Type I) noise in the mixer output. (SWR)^ = Signal-to-noise associated with non-memory type (Type 2) noise in the mixer output. T = Measurement interval. W1 = Bandwidth of the type I noise. Memory noise (Type l) is associated with noise generated within the oscillator generating the signal to be translated. Won-memory noise (Type 2) is associated with noise which, originates between the 29 basic oscillator and the oscillator unit output terminals. The mixer will not be able to distinguish between the two types of noise and both signal-to-noise ratios in the mixer output will be reduced by the same amount. 3.3 FREQUENCY MULTIPLICATION. ■ In this section the general properties of an ideal frequency multiplier are discussed. It will be pointed out that the fractional frequency stability in the output of the ideal frequency multiplier is the same as the stability of the input signal. Consider a device whose input-output relationships are as shown in Fig. 3-5, with the input v^(t) and output Vg(t). Consider an ' ! input 9 V1 Ct), to the multiplier of the form (t) = A cos WQt, (3-22) V1 Ct) Fig. 3-5. IDEAL FREQUENCY MULTlFLIER. 30 Then the output of the frequency multiplier is V2 (t) = A 1 cos nw^t. (3-23) where A 1 = fixed amplitude related to A by a constant (A' = kA) n = desired harmonic (integer > l) .The means of obtaining the desired frequency multiplication under consideration here is that of employing a nonlinear device. The input signal is applied to the nonlinear device to generate the n**1 harmonic of the input frequency w . The input-output- relationship of the device is expressed as where a = constant of the device n n = desired harmonic Consider an input, v^(t) to this multiplier as given by V2 (t) = an [V1 (I)Jn (3-24) V1 (I) = A cos w^t Then the output from the frequency multiplier is (3-25) Vg(t) = a^ [A r u 4 w_t]n . th The n harmonic terms at the output is (3-26) . a A n (3-27) 31 How let the input signal also contain a noise voltage as discjissed in Sec. 3.1, and given "by (3-4). The output of the multiplier as a result of adding signal and noise is V2 (t) = an [(A + v (t)) cos W^t + v (t} sin Wgt]n . (3-28) The input signal-to-noise ratio to the multiplier must he very large if it is to yield a narrow spectrum after multiplication in frequency synthesis systems. Assuming a large signal-to-noise ratio the output of the multiplier neglecting the nonlineaer noise ( terms can he expanded and expressed as V2 (t) = an [(An + nAn_1.vc (t)) cos nW^t + nA11-^ v (t) cos11 1 W t sin w t] (3-29) s o o The U bh harmonic term at the output is .a .n-1 v„ (t) = ---- -— [A cos nw t + nv (t) cos nw t 2n 2n-l o c - o + nvg (t) sin nwQt ] (3-30) The signal-to-noise ratio at the output can he expressed from (3-30). as (SHR) A2 ° n2 (vc (t)2 + Vs (t)2 ) = ~ (SHR)i . n (3-31) 32 Where (SNR)^ = Signal-to-noise ratio at the input (SNR)o = Signal-to-noise rat'io at the output. 2 Thus the noise power has' "been increased by n , the multiplication factor squared, relative to the output .signal power. In Appendix A the fractional rms frequency deviation of an oscillator output signal is given as Sr (SNR)1T I " (SNR)2T' il/2 (3-32) The short-term stability of the output signal (after multiplication) can be expressed as 3Tn ,1/2 (SNR)nlT (SNR)^T' (3-33) where (SNR)nl = Signal-to-noise ratio associated with memory type noise in multiplier output (SNR)^2 = Signal-to-noise ratio associated with non-memory type noise in multiplier output. Since the multiplier will not be able to distinguish between input noise sources both signal—to—noise ratios will be decreased by the square of the multiplication factor. Thus, (3-33) becomes (3-34) (SNR)2 T n2 . vhich reduces to ^ n = S?" Therefore, the ideal multiplication process does not alter the input oscillator stability. It is shown in the Appendix B that for a higher order transfer characteristic than required, the output signal-to-noise ratio is degraded .more than that of the n^*1 order characteristic discussed here. It is shown there that the orders contributing to this degradation are the a^ + 2j for «3 > 0° 3.4 FREQUENCY DIVISION. In this section the general properties of an ideal frequency divider are discussed. It will be shown that the frequency stability of the output of an ideal frequency divider is the same as the stability of the input. Consider a device whose input-output relationships are as shown in Fig. 3-6. First, consider the device driven by a perfect input signal (noise being excluded) expressed by v^(t) = A cos w^t (3-35) 3k •5s» V2 (t ) Fig. 3-6. IDEAL FREQUENCY DIVIDER. with fixed, amplitude A and frequency Wq . The frequency divider will produce an output signal V9 Ct) expressed as . .CO t V0 Ct) = A 1 cos —2— . (3-36) where n is an integer and A ’ = kA. This device is also referred to as a. divide-hy-n or n-divider. Now let the input signal also contain a noise voltage term. The input signal v^(t) for this case as discussed in Sec. 3.1 is V1 Ct) = B(t) cos [to t + <|>(t)] -L O = B(t) cos <#>' (t). (3-37) For this v^(t) the divider output V 2 (t) will be expressed as v2 (t) = B 1 (t) cos [ ~ - + ^ b-- I (3-38)- where again n is an integer and B ’(t) = kB(t). From this definition of an ideal frequency divider two charac- • teristics are apparent. First, that it is the instantaneous 35 frequency not the Fourier components that is being divided by the number n-. In equation (3-37) B(t) and '(t) are real functions of time. For signals of interest here, the signal-to-noise ratio will be large and therefore, ■ B(t) will be essentially a constant. For this assumption B(t) will contain none of the zero crossing of (t), and tj)’ (t) is defined as the instantaneous phase angle of deft' (t) dt v (t), and a), (t) = is by definition the instantaneous ----- i frequency. The amplitude function B(t) is the instantaneous amplitude and the magnitude of B(t) is termed the envelope. Second, the frequency divider will leave a constant-envelope input signal unchanged except for a constant scale factor. From (3-38) and the expression for the fractional short-term stability (A-21) given in Appendix A, it follows that the stability of the input signal after frequency division is not affected by the ideal frequency division process. It.O MALYSIS u D Y f r v x l j 7 f 4 l x n f 4 Y l 0 g Y f p ' The availability of new semiconductors with highly refined performance characteristics has made the re-evaluation of common design approaches necessary. Several semiconductor devices now available yield system functions with significantly increased per­ formance levels and in many cases will provide system simplification. Techniques that employ several of the new semiconductor devices will be analyzed. The major characteristic desired in the techniques investigated is that of broadband input and output frequency characteristic while performing a specific circuit function. If the circuit operation does not naturally have this characteristic then it is desirable that it be capable of providing the required broad­ band operation by employing rapid electronic switching or tuning. The discussions in this chapter are classed under the three signal operations presented in Chapter III. Parametric harmonic generators which use high Q input and output filters have been omitted from the discussions. Only two sinusoidal voltages are allowed to exist across the nonlinear capacitance. One voltage appears at the fundamental frequency, w, and the other voltage appears at the n^*1 harmonic, nio. All other frequencies are shorted out. Analyses presented in the three references [9], [lO], and.[ll] establish minimum and maximum efficiency levels for the varactor multiplier restricted to reverse bias operation. ■u.l SEMICONDUCTOR DEVICE CHARACTERIZATION. The diodes used in the analysis presented in sections 4.2, 4.3, and 4.4 are classed as ideal nonlinear resistances or ideal nonlinear reactances. The ideal.nonlinear resistance is approximated "by the old work horse, the point contact diode and the more recently developed Hot Carrier or Schottky Barrier diodes. The ideal nonlinear reactances are approximated "by the varactor diodes designed either for strictly reverse bias operation or forward conduction. I The ideal nonlinear resistor diode is a perfect rectifier as the V-I characteristics shown in Fig. 4-1 indicate. It is character­ ized by a devide with zero resistance under forward bias and with an infinite, resistance under reverse bias. Another important characteristic of the perfect rectifier which is not pointed out by Fig. 4-1, is that the device exhibits zero capacitance. The capacitance referred to being either device case capacitance or a capacitance associated with the storage of conduction carriers. The ideal nonlinear capacitance may be characterized as shown in Fig. 4-2. This is a charge (q) vs voltage characteristic. The nonlinear capacitance is characterized by an infinite capacitance under forward bias and zero capacitance under.reverse bias, with complete "recovery of charge when the voltage drops to zero. VFig. U-I. IDEAL NONLINEAR RESISTOR CHARACTERISTICS. Fig. U-2. IDEAL NONLINEAR CAPACITOR CHARACTERISTICS. 39 k.2 MULTIPLICATION. Frequency multiplication using the nonlinear resistor has been developed by C. H. Page [12]. His results give an expression for the maximum harmonic generation efficiency as Pi = Po + I P' > I n2P' > n2Pu ri — ■ k n — r n>l n>l (A-I) where P^ = power generated at the n harmonic P^ = fundamental power yj =■converted dc power. For any specific value of n, two relations may be obtained from (4-1) as ■ I Pn - P i n (4-2) and • P- > ’(n2-l) P (4-3) o — n 2 Equation (4-2) gives the maximum efficiency limit as l/n for the condition of all other harmonics being zero. Equation (4-3) shows that the remaining fundamental power (when equality holds) is converted to dc. Greater efficiency can be expected for the'nonlinear capacitor since the device would not rectify and hence input power conversion to dc power is eliminated. Manley and Rowe [13] have derived the general set of power flow relationships for an ideal nonlinear reactance in a general circuit configuration using ideal filters. The equation they obtained are I ■ I .mP m , n . Hif1-Hnf2 0 ( M O I • I n=0 m=-00 nP m,n Mf1-Hnfg 0 (M) where Pm,n is the power flow into the reactance at frequency Inf1 and nfg. These relationships.are independent of the shape of the non­ linear characteristic and the power levels employed. With proper filtering, these relationships predict that a lossless nonlinear reactance used in a harmonic generator configuration has a conversion efficiency of 100%, regardless of the harmonic involved. To illus­ trate this result, consider power flow allowed only at two frequencies one being the fundamental frequency (f) and the other the desired harmonic (nf). Equation (h-4) then reduces to where . . . yj = power at f (supplied by input generator) P^ = power at nf (delivered to output load). (4-6) Equation (4-6) gives Pn/P = -I which indicates the 100% harmonic conversion efficiency, independent of the multiplication order n . The discussion thus far has served to set the theoretical limits of harmonic conversion efficiencies obtainable depending upon the nonlinearity employed. In the sections that follow, discussion will focus on techniques which perform the multiplication function but whose maximum theoretical conversion efficiencies fall short of upper theoretical limits. For a set of system specifications, these less efficient techniques may be dictated in the system realization by such factors as cost, size, tuning speed, etc. 4.2.1 RECTIFIER DIODE HARMONIC GENERATOR. Two broadband rectifier diode circuit techniques to be analyzed are the clipped sine wave generator and the full wave rectifier. The equivalent circuits for these generators are shown in Fig. 4-3. The analysis of the clipped sine wave generator is given in Appendix C. The theoretical conversion loss for the harmonic frequency components appearing across R^ are shown in Fig. 4-4, and Fig. 4-5, as a function of the half-conduction angle 0. The curves presented in Fig. 4-4 are for the even order harmonics of the input frequency and those presented in Fig. 4-5 are for the odd order harmonics. k2 (a) Cb) Fig. 4-3. RECTIFIER GENERATOR EQUIVALENT CIRCUITS. (a) Clipped sine wave generator ("b) ■ Fnll wave rectifier. The data presented was calculated on one degree increments using a digital computer. I . Figure 4-6 presents the minimum conversion loss associated with each harmonic as taken from the computed data. The minimum loss associated with the even order harmonics occurs for 0 = 90° and the numbers associated with each odd order graph entry indicate the value of 6 at which their respective minima occurred. k3 F i g . 4 - 4 . C L I P P E D S I N E W A V E O U T P U T S P E C T R U M n E V E N . F i g . 4 - 5 . C L I P P E D S I N E W A V E O U T P U T S P E C T R U M n O D D in db H a r m o n i c N u m b e r n F i g . 4 - 6 . M A X I M U M S P E C T R U M A M P L I T U D E - C L I P P E D S I N E W A V E G E N E R A T O R . The harmonic spectrum of the full wave rectifier can he obtained from the half wave rectifier spectrum (0 = 90°) by adding 6.02 db to the even order values. These values are also presented in Fig. k-6. The deviation from the maximum efficiency, 10 log l/n , can be determined directly for either the clipped sine wave or full wave rectifier generators. The curve at the bottom of Fig. U-6 indicates how this type of generator might be used when a braodband spectrum is desired. If a half-conduction angle 0 = 8U° were used the odd-order harmonic spectrum, 3rd to 19th harmonic, would vary less than 10 db from the maximum attainable output. For an even and odd high order harmonic spectrum of a particular characteristic an angle 0 between 85 and 90 degress would be used. As indicated in Fig. U-6 the most efficient of the techniques under consideration here is the full wave rectifier used as a frequency doubler, n = -2. U.2.2 BROADBAND NONLINEAR CAPACITOR HARMONIC GENERATOR. The'broadband-harmonic generator has been analyzed by Leenov and Uhlir [lU]. The equivalent circuit for the broadband nonlinear capacitor harmonic generator is shown in Fig. 4-7. The diode used .in this analysis has infinite capacitance under forward bias, complete recovery of charge when the voltage drops to zero and zero ; capacitance under reverse, bias. nonlinear capacitor Fig. 4-7c BROADBAND HARMONIC GENERATOR EQUIVALENT CIRCUIT, : ' i The analysis of this harmonic generator is presented in Appendix D. The theoretical conversion loss for the harmonic frequency components appearing across R^ are shown in Fig. 4-8 and 4-9 as a function of the half-forward conduction angle 8. The curves presented in Fig. 4-8 are for the even order harmonics of the input frequency and those presented in Fig. 4-9 are for the odd order harmonics. This data was computed on ten degree increments using a digital computer. Figure 4-10 presents the minimum conversion loss associated with each harmonic as taken from the computed data disregarding the in d b 6 i n d e g r e e s F i g . 4 - 8 . N - C H A R M O N I 5 S P E C T R U M n E V E N -E- OO in d b Q i n d e g r e e s P i g . 4 - 9 . N - C H A R M O N I C S P E C T R U M n - O D D PL n in db •C G e n e r a 1 4 1 8 H a r m o n i c N u m b e r n F i g . 4 - 1 0 . M I N I M U M C C N Y Z R S I C N L O S S F O R N - C G E N E R A T O R 51 conduction angles required for these minima. Comparison of Fig. k-6 and 4-10 will indicate the superior performance of this "broadband generator to the rectifier diode generator. This efficiency advantage increases as higher order harmonics are considered. 4.2.3 BROADBAND STEP RECOVERY DIODE HARMONIC GENERATOR. In harmonic generation, where the diode is operated with inter­ mittent forward conduction, the performance will depend on minority carrier lifetime, r, and the junction retarding field as discussed in reference [15]• Minority carrier lifetime determines the amount of stored charge that remains in the junction at the onset of reverse recovery and the rate of carrier recombination during recovery. The junction field determines the stored charge available for removal during storage conduction. For a minority carrier lifetime of zero, the diode characteristics are those of a nonlinear resistance as used in the analysis of 4.2.1. If the minority carrier lifetime is assumed infinite, the diode character­ istics are those of the nonlinear capacitance used in the analysis of 4.2.2. This section is concerned with the broadband harmonic generating characteristics associated with, the class of diodes having high junction,retarding fields and finite carrier lifetimes. The broadband analysis presented here parallels and analysis presented by Krakauer [l6], with.many graphical additions which give 52 a clearer understanding of the multiplier performance as S Y and are varied. The equivalent circuit and steady state current waveform for this analysis is shown in Fig. 4-11. Circuit current starts to flow at- art = 6 when the input voltage overcomes the bias voltage, V, plus the diode barrier voltage; ijj. Diode current flows until art = 0 + at which time the stored charge has been depleted. Fig. 4-11. SRD BROADBAND MULTIPLIER EQUIVALENT CIRCUIT AND CURRENT WAVEFORM. 53 ■ The relation between 0 and <}> is derived in Appendix E and is expressed as -/0}T Tan 6 sin + MTe -MT sin (J) - cos + M^ T^ (l-e 5l (U-T) where M = input frequency T = minority carrier lifetime 0 and (J) as indicated in Fig. U-Il. Values for 0 were computed, for e Y values between 0.1 and 1,000,000, as a function of . The results are presented in Fig. U-12. As illustrated, the e Y dependence is essentially eliminated for e Y > 10. The harmonic spectrum conversion loss associated with the current waveform of Fig. U-Il is also presented in Appendix' E. The calculation was carried out using a digital computer. Several graphs of the computed data are presented for various value of e Y H Fig. U-13, U-lU, U-15, U-l6 are the harmonic spectrum presentations for MT = 3.0. Fig. U-IT, U-l8, U-19, U-20 are the presentations for MT = 10.0, and Fig. U-21, U-22, U-23, U-2U are for e Y = 100.0. - Fig. U-25 presents the minimum conversion loss associated , with each harmonic disregarding the condition angle, (J), required for these minimums. The dependence of the generator conversion loss as a function of the e Y product is.clearly illustrated. <$> I n d e g r e e s Q A N D 0 F O R S R D M U L T I P L I E R in db 55 H a r m o n i c N u m b e r n Fig. 4-13. SRD HARMONIC SPECTRUM uvr = 3.0. I 56 H a r m o n i c N u m b e r n Fig. 4-14. SRD HARMONIC SPECTRUM w T = 3.0. 57 4-44- H a r m o n i c N u m b e r n Fig. 4-15. SRD HARMONIC SPECTRUM wr =3.0. QP uf Uid 58 H a r m o n i c N u m b e r n F i g . 4 - 1 6 . S R D H A R M O N I C S P E C T R U M W T =3.0 59 H a r m o n i c N u m b e r n Fig. 4-17. SRD HARMONIC SPECTRUM U/T= 10. PL n in d b 60 F i g . 4 - 1 8 H a r m o n i c N u m b e r n S R D H A R M O N I C S P E C T R U M u / T = 10 H a r m o n i c N u m b e r n Fig. 4-19 SRD HARMONIC SPECTRUM WT = 10 H a r m o n i c N u m b e r n Fig. 4-20 SRD HARMONIC SPECTRUM w r =10 Pi n in d b 63 H a r m o n i c N u m b e r n Fig. 4-21. SRD HARMONIC SPECTRUM u / T = 100, PL n in db I 65 -H-H H a r m o n i c N u m b e r n F i g . 4 - 2 3 . S R H H A R M O N I C S P E C T R U M W T =100 66 Fig. 4-24. SRD HARMONIC SPECTRUM ujT =100. 67 H a r m o n i c N u m b e r n Fig. 4-25. SRD MINIMUM CONVERSION LOSS. 68 ■ Another set of curves can be presented from the computed data •which.indicate more clearly the conversion loss dependence for a specific harmonic as a function of A set for even and odd order harmonics for umY = 3.0 are given in Fig. h-26 and b-2J respectively. Still another graphical presentation which relates harmonic • number, conversion loss variation and ’,may be presented as in Fig. 4-28. This presentation along with that of Fig. 4-25 would present, the necessary design information for a specific application. Curves similar to those of Fig. 4-28 were drawn for umY N LHE• 10, 100, and 1000. If the design application can tolerate a deviation from the minimum conversion loss presented in Fig. 4-25 then will have a range of values. The range, of cj> for selected deviation levels of I and'3 db of the minimum conversion loss as a function of WT are given in table 4-1. The diode discontinuity for this analysis was assumed to be instantaneous. In the practical multiplier a finite transition time, t^ ., exists. The effect of this on the harmonic generation will be discussed in Chapter 5. 4..2.4 STEP RECOVERY DIODE HARMONIC GENERATOR WITH RESONANT LOAD. Replacing the load resistance in the multiplier circuit of ■ Fig. 4-11'with a resonant load yields a significant increase in the conversion efficiency at the harmonic associated with this Harinonib N u m b e r UU i c.uu i n D e g r e e s Fig. 4-26. CONVERSION LOSS vs 0 n EVEN in db i n D e g r e e s Fig. 4-27. CONVERSION LOSS vs n ODD. Ha rm on ic N um be r I-H LI Lhid L L L r . C *> T U I I _ -t - =4444- + F T, I t 1 ! H - JLCL^g ±H44- - -LU - rl - d U -4-4-_ _ 4-i- D x pm 6 C - d- - - - -C =C =] -" ZT _ L E — 4- =C - -|- ~ - - rff ■ " = - U v -C 111 - - T T - —j— T T T d . t- - d I— ± T T C= Z ± - . ZL 4= l=ciT : Ii . TL — _L Z - T C T T =C -f- - - — - r -4- T T zFJ- T T Ii FT = 4 - - - - T ± T— --=C L- - -=F T TU-L-U _=c I | 11 T ZCC_L -T 1—1 . H I L u ru " T11 , I I I I M CL TI I I I I—I— 100 200 cb i n D e g r e e s Fig. 4-28. RANGE OF . 300 72 Table 4-1 RANGE OF WT I db ' 3 db 1.0 175-255 P |v C O 3.0 225-235 n >_ 13 175-275 n >_ 6 10.0 225-240 O 1—IAlG 175-280 VOAlfl 100. 225-240 n >_ 10 175-280 n > 6 1000 225-250 n >_ 9 175-280 n > 6 resonance. An analysis of this type of multiplier [ij] has "been presented which allows its performance to he determined. The discussion that follows will parallel this analysis with several graphical additions which give a clearer understanding of circuit parameter variation on multiplier performance. The equivalent circuit for the harmonic generator with a resonant load is shown in Fig. 4-29« In this analysis, only exponentially decaying sinewave outputs are considered. The circuit shown consists of an ac driving source and source resistance in series with a bias source V.driving the SRD diode and the parallel resonant circuit. The diode,for this analysis is considered to be an ideal nonlinear capacitor. For S Y > 10 this idealization is reasonable. TB R SRD A sin (orb - 6) Fig. 4-29. EQUIVALENT CIRCUIT OF HARMONIC GENERATOR WITH A RESONANT LOAD. Harmonic energy is generated "by this circuit in the following sequence. When the diode is forward biased, current flows through the circuit. Diode conduction is sustained until the charge that has passed through it becomes zero. The diode then ceases to conduct leaving a current, I, flowing in the inductance L. With the diode cut off the energy stored in the inductance is dissipated in the load. It is assumed that the circuit starts from rest for each conduction state. This requires that the energy in the resonant circuit be dissipated by the time the next conduction interval begins. The analysis of this multiplier is given in Appendix E. Two conversion efficiencies are defined, which when combined yield the overall performance of the multiplier. One efficiency is defined in terms of the conduction characteristics and is expressed as Pri = 10 log [ - U L - ] db . (4-0) L1 OQ1I2 where E = amplitude of driving source Rg = generator source resistance I = current in the inductance at the end of the diode conduction. Values for this relationship were computed, for values between .1 and 80, as a function of . The results are presented in Fig. 4-30 and Fig. 4-31. ■ The relationship between 0 (angle of diode current initiation.) and <|> (angle at which diode current ceases) is given in Fig. 4-32. . The second conversion efficiency is defined in terms of non­ conducting state and for the desired harmonic is expressed as PL2 = 1.96 - 10 log [ [1-e-n/Q2^-'f>/2 )]2]. ah. (4-9) where Q2 = nwC Rk n =•harmpnic number nw = (L C )“li/2 75 Values for this relationship were computed, for Q^/n values between o 2 and 2 as a function of tf>. These results are presented in Fig. 4-33. From Fig. 4-30, 4-31, and 4-33 the overall conversion loss, Prp, for the harmonic generator can he determined by adding the two appropriate conversion losses for a given conduction requirement. From the value of 0 can be determined and therefore, the bias voltage V. From the computed values, conversion loss characteristics as functions of and Q^/n were determined. These characteristics are plotted in Fig. 4-34 and 4-35• It can be seen from these curves that the minimum value of P 1^ is 8.5 db. This minimum occurs for = 1.2 and Q^/n =0.8. In designing multipliers of this type, these two sets of curves may readily be used to set limit's on circuit values to be used where an acceptable P^ is specified. In the design of a multiplier, variation of the conduction characteristic and the resulting performance, degradation are of considerable interest. Table 4-2 presents the degradation expected- for stated range of and specific values of Q . This table was generated by considering all values of between 0.1 and 2.0 and letting the corresponding minimums set the range of to be considered. This table then places a lower tolerance level on each curve of Fig. 4-35. Pl 1 in d b Fig. 4-30. CONVERSION LOSS Q 1 =.! to 1.0 R-L SERIES CIRCUIT. in db 4> i n d e g r e e s Fig. 4-31. CONVERSION LOSS Q 1- I .6 to 80 R-L SERIES CIRCUIT in de gr ee s X cj) i n d e g r e e s Fig. 4-32. Q AMD cj> CONDUCTION CHARACTERISTICS QP UT Z rIj 100 200 300 0 i n d e g r e e s Fig. 4-33. e ■ a r Z X P O Q Z n I a g I A I g FBS Q ■ a ■ g g I g O P a O T P R V PT In d b Fig. 4-34. MINIMUM CONVERSION LOSS AS A FUNCTION OF Q 1 . I t I T Fig. 4-35. MINIMUM CONVERSION LOSS AS A FUNCTION OF Q2Zn, -LL-IL ' 82 . . Table k-2 OVERALL CONVERSION EFFICIENCY DEGRADATION .Variation.(deg.) HyY Variation.Cdb) ■ 0.1 . 240-200 1.0 0.2 245-205 1.13 0.4 255-210 1.33 0.6 265-215 1,66 0.8 270-220 1.75 1.0 275-225 1.92 1.2 280-225 2.15 1.4 285-225 2.47 1.6 285-230 2.34 1.8 290-230 2.74 2.0 290-235 2.65 5.0 300-240 3.24 10.0 305-240 3.68 20.0 305-240 3.58 40.0 305-240 3.53 80.0 305-240. 3.5 4.3 DIVISION . A variety of circuit techniques have been used for many years to provide frequency division. These techniques . ' . ; are classed under ■ v-" ••■■■■ 83 the categories of relaxation, counter, or sinusoidal devices. The relaxation divider accomplishes division by the premature termination of its natural period due to the injection of a signal to be divided in such a manner that synchronization is maintained. Reliable operation of the relaxation divider is limited to frequen­ cies of several MHz. The digital counter operation is normally that of a frequency divider. The counter output is generated as a function of the . required number of input pulses. The advantage of this type of divider is that of wide integral division ratios and ease of changing this ratio either electronically or by switches. At present the upper frequency limit of these dividers in solid state integrated packages is 150 MHz. Sinusoidal dividers are used for division at higher frequencies. The regenerative dividers, locked oscillator divider and parametric diodes are employed at the higher frequencies. In general the operational frequency range of these dividers is limited by the tuned circuits employed. The locked oscillator divider has the advantage of simplicity over the regenerative divider and some forms of the parametric divider but has the major disadvantage of providing an output with the loss of the synchronizing signal. Parametric oscillators of the type which satisfy the Manley S Rowe relationship discussed in Chapter 3 have been, discussed by 84 Hilibrand and Beam [l8] for order 1/2. This type of divider requires- input and out filters tuned at frequency co and aj/2 respectively. Due to the filters, this divider has a limited operational frequency range. Hedderly [19] and Ryan and Williams [20] present analysis for parametric dividers possessing wide operational frequency range. The results of their analysis are illustrated for the case of subharmonic oscillations of order 1/2. In the first analysis [19] infinite diode lifetime is assumed and in the second analysis [20] the analysis is for cot <_ I. Analyses predicts octave operational frequency bandwidth. In both analyses the load and generator resistances are ignored. In the broadband divider circuit presented in the next section both load and generator resistances are included. Analog computer simulations presented pr,edict broadband operational frequency range for a division ratio of 1/2. 4.3.1 BROADBAND STEP RECOVERY DIODE FREQUENCY DIVIDER. The divider presented in this section was an out-growth of several broadband input diode multiplier circuits and experimentation with the two broadband frequency dividers mentioned previously.. The divider executes subharmonic oscillations of order 1/2 and has an operational bandwidth greater than an octave in frequency. The circuit for the divider is shown in Fig. 4-36, and consists 85 of an ac generator in series with the reactive T-section of C and L1S driving a SRD diode in series with the load resistance. Fig. U-36. BROADBAND DIVIDER EQUIVALENT CIRCUIT. The more popular method of finding the solutions for the circuit equations in circuits of this type is to assume piecewise- linear operation. The method of approach is to assume a piecewise linear representation of the nonlinear element, solve the circuit equations for the linear regions, and match these solutions at appropriate houndries of operation. The difficulty with this approach is that, while the equations in general may be easily set upj they are usually difficult to solve. This difficulty exists for systems with only one conducting and one nonconducting state. 86 For this discussion the SRD diode in Fig. k-36 is assumed to be an ideal nonlinear capacitance. As discussed in Section 4.1, its operation is described in terms of the charge flowing through it and the voltage across it. An attempt was made to solve the circuit equations describing the operation of the circuit of Fig. 4—36. While the equations are relatively easy to set up, a general solution for two linear regions of operation was not obtained. The analysis in general cannot be restricted to the case where all conducting and,nonconducting states are, respectively, identical. The divider circuit operational waveforms shown in Fig. 4-38 to 4-44 were obtained by analog computer simulation, v^ appearing at the top of Fig. 4-38 to Fig. 4-43 is dv^/dt. v-^ is the required input for the analog simulation and this waveform was recorded to provide a timing reference. The circuit of Fig. 4-37 was used to generate the set of system equations to be simulated. The exchange of circuit placement of R and C from that of Fig. 4-36 was required to remove an oscillation that appeared in the simulation of the circuit of Fig. 4-36. Also a value of capacitance has to be assumed' for Cg, the stray-wire circuit capacitance. An analysis of this divider given in Appendix F was used in the analog computer simulation. The values used for the two inductors, ■ L, and the input capacitor, C, were calculated for divider action 87 Fig. 4-37- DIVIDER EQUIVALENT CIRCUIT USED FOR ANALOG SIMULATION. in the 500-1000 MHz frequency range. The value for the stray-wire capacitor, Cg , was assumed to he.2 pf. The three frequencies of 500, 750, and 1000 MHz were selected to obtain typical circuit waveforms and operational power level. Fig. 4-38 and Fig. 4-39 show the divider waveforms associated with the circuit of Fig. 4-37 for an input frequency of 500 MHz. Fig. 4-40 and Fig. 4-4l present the 750 MHz circuit waveforms, and Fig. 4-42 and Fig. 4-43 present the 1000 MHz operation. The operational frequency thresholds are shown in Fig. 4-44. At both end limit frequencies the circuit barely sustains the sub­ harmonic oscillation. 88 Fig. 4-38. DIVIDER WAVEFORMS 500 MHz OPERATION. O O 89 F i g . 4 - 3 9 . D I V I D E R W A V E F O R M S 5 0 0 M H z P O W E R - F R E Q U E N C Y C H A R A C T E R I S T I C S . O M 90 I n p u t P o w e r 1 3 . 3 d b m Fig. 4-40. DIVIDER WAVEFORMS 750 MHz OPERATION. O O 91 F i g . 4 - 4 1 . D I V I D E R W A V E F O R M S - 7 5 0 M H z P O W E R - F R E Q U E N C Y C H A R A C T E R I S T I C S . 92 I n p u t P o w e r 8 d b m Fig. 4-42. DIVIDER WAVEFORMS 1000 MHz OPERATION. O O O O O O F i g . 4 - 4 3 . D I V I D E R W A V E F O R M S - 1 0 0 0 M H z P O W E R - F R E Q U E N C Y C H A R A C T E R I S T I C S . F i g . 4 - 4 4 . D I V I D E R F R E Q U E N C Y C H A R A C T E R I S T I C S . ■95 In all cases for the waveforms presented, the circuit was considered to he in a steady state condition while executing the subharmonic oscillation of order 1/2. The determination of the steady state condition was determined by visual monitoring of the computer output. In some cases, especially at the end limit fre­ quencies , 15 to 50 cycles of the driving wave form were required before synchronism was established. Fig. 4-45 shows the operational power level range for two bias conditions. Power levels for proper divider action consist of the area between the two curves for a given bias condition. In the design of a divider for a specific octave frequency range a method to determine the values of the two inductors and the input capacitor is required. The relationship used to determine the values of L and C are expressed as 1.4l421 R C = 1.41421 V g (4-io) where is the upper frequency of the octave range desired. The designer familiar with normalized filter coefficients will recognize the relationships of (4-10) as those of maximally flat low pass filter with equal resistance terminations.« T O M F r e q u e n c y i n M H z F i g . 4 - ^ 5 . D I V I D E R O P E R A T I O N A L P O W E R L E V E L 97 k.U TRANSLATION' In the case of frequency translation the isolation of the signal and translating frequencies in the mixer output may he adequately provided by means of filters to separate these unwanted signals from the desired signal. For the case requiring isolation of either or both of these frequencies, the singly and double balanced mixer are a means of easily providing the required rejection. The advantages• of using the double balanced mixer were discussed in Chapter 3. 4.4.1 BROADBAND DOUBLE BALANCED MODULATOR. The double balanced modulator performance was analyzed in the mixer performance discussions of section 3.2.4. The analysis presented in 3.2.4 pointed out the superior spurious component generation characteristics of this type of mixer over the common diode mixer and the singly balanced mixer. The characteristics of the double balanced modulator can be realized with many different combinations of transformers and diodes. The configuration shown in Fig. 3.4 for the modulator realization is one of the simplest forms. The superior spurious level performance of this modulator relies on several factors. If the signal voltage unequally varies the current in the diode sets then unbalance will occur. If the translating signal is not a symmetrical waveform, an unequal current- time relationship will be introduced causing distortion products 98 even though the translating frequency remains balanced.■ The trans­ formers used must have a high degree of balance, and this balance relies heavily on the physical symmetry of the transformers. The physical layout of the transformer becomes very important for high frequency operation. Balance of the diodes employed must be main­ tained over the entire forward conduction characteristic required. The modulator power-handling specification will dictate the magnitude of this range. Diodes used are of the rectifier type with . minimum conduction storage characteristics. The conversion loss for this double-balanced modulator is calculated in Appendix G . • The calculation is made assuming a balanced circuit, ideal rectifier diodes and a square wave switching voltage. A conversion loss of 3.92 db is calculated for either of the desired sum or difference frequency products. This value will be used in comparing the performance of the modulators presented in Chapter 5- J5-0 EXPERIMENTAL RESULTS ' The implementation and testing of the techniques of Chapter b was carried out to determine the practihility and repeatability of these techniques. It should be kept -in mind that the combinations y of the signal operations, used in a synthesis scheme for one . application will not necessarily be those employed for another, even though the frequency range of operation may be essentially the same. For example, in one system the efficiency of the rectifier diode harmonic generator (as inefficient as this method is) may be suffi­ cient for the frequency multiplication requirements. In another system the efficiency required may dictate the uses of the harmonic generator with a resonant load which is either made up of switched filters of different center frequencies or one electronically tunable filter. As will become apparent from the performance data presented, the frequency range of operation of the circuits tested is from 10 MHz through 2 GHz with the input circuit having maximum operational bandwidth. The reasoning behind this requirement is that broadband input circuitry eliminates operational tuning over a specified frequency range. The diodes used in the construction of the rectifier harmonic generators and the full' lattice modulator were of the hp 2900 type which employ a metal-silicon barrier junction and utilize electrons for majority carrier conduction. The low capacitance wbj = 1.2 pf) '■ " 100. . and short minority carrier lifetime allow the use of this diode from low frequencies through the UHF range. The characteristics of the step recovery diodes used in the various multipliers and dividers are given in Table 5-1• The diode parameters tabulated are capacitance COq ), effective minority carrier lifetime (x), and transition time (t^ _). The capacitance, Cq , is measured with zero applied voltage and a frequency of I MHz. The minority carrier lifetime is not a constant but is dependent upon both drive level and temperature. From the diode specifications this may increase 50% in the circuit investigated. 5.I MULTIPLICATIOH. In this section the experimental work that was performed with the various methods of obtaining frequency multiplication discussed in Chapter 4 are presented. In order to obtain a very broadband coupling circuit, consider­ able effort was expended on development of a low-power transformer. Many different ferrite materials were investigated along with a variety of toroid dimensions and winding configurations. The material finally used was the 3E2A Ferrite material manufactured by Ferrocube. The large initial permeability (5000 at 25°C) of the 3E2A material requires fewer turns for a given low frequency response. Windings investigated consisted of a twisted pair of Formex wire for 101 Table 5-1 DIODE PARAMETERS Type CoPf rns(min) . t . ns t 0102 20 100 2 0103 20 250 5 0112 3 50 ' ' 0.3 0114 10 125 ' 0.4 0151 1.6 ■ 20 0.15 the single primary-single secondary transformers and of twisted three-strand and parallel three-strand (fastened together in' a triangular configuration) for the unbalanced-to-balanced transformers. The parallel three-strand Formex #U0 wire windings on a .190 outside diameter 3E2A toroid core gave the best results. For frequencies of operation below 10 MHz and up to several hundred MHz, 7 to 10 turns was found to provide the necessary coupling for efficient operation. For operation above 10 MHz, 3 to 4 turns was found to be sufficient. . 5.1.1 RECTIFIER DIODE HARMONIC GENERATOR. The two braodband rectifier diode harmonic generators constructed I 'are shown schematically in Fig. 5-1. The diodes employed in these generators were the type hp 2900. 102 I o v C v (a) Clipped Sine Wave Generator Cb) Full Wave Rectifier Generator Fig. 5-1. RECTIFIER DIODE HARMONIC GENERATOR CIRCUITS. Data obtained for the clipped sine wave generator employing a U-turn and 7-turn transformer, are presented in Fig. 5-2 and 5-33 respectively, for an input power level of 20 dbm. The solid curves are drawn for the zero bias condition ("V = 0). • Comparison of these two data sets will show the high frequency superiority of the U-turn transformer circuit over the 7-turn. The .deviation of U-8 db of the data presented in Fig. 5-2 from that predicted in Section U .2.1 can be accounted for by considering, transformer losses, circuit and diode capacitance and finite diode impedance under forward conduction. The dashed curves were obtained by adjusting the bias voltage, V, to obtain optimum output at the harmonic being measured. Again the U-8 db deviation from the predicted levels can be observed. 1200 O u t p u t F r e q u e n c y I n M H z F i g . 5 - 2 . C L I P P E D S I N E W A V E H A R M O N I C G E N E R A T O R O U T P U T . 1 0 3 in db Fig. 5-3. CLIPPED SINE WAVE HARMONIC GENERATOR OUTPUT. 105 For the measurements made on this generator and in general for all the various experimental circuits tested refer to Fig. 5-^. The desired power level from the signal source is adjusted by monitoring the voltage across the 50 ohm load. With the desired maximum available level set, the signal is applied to the device under test. The output is then monitored on either a spectrum analyzer or a sampling oscilloscope. The two attenuators are used to insure that the output impedance of the generator and the termina­ ting impedance are both approximately 50 ohms. 50 ohms Generator Signal Attenuator Attenuator Circuit Under Test Voltmeter Sampling Oscilloscope Fig. 5-4. MEASUREMENT DIAGRAM. 106. Data obtained for the full wave rectifier generator is presented in Fig. 5-5 and Fig. 5-6 for 8-turn and 3-turn transformer windings respectively. From the data presented the second harmonic conver­ sion loss is typically 15 db or less for input frequencies through 700 MHz. The suppression of the fundamental and third harmonic are at least 18 db and 25 db below the output power level respectively The output level available over the efficient doubling range approximately 5 to 6 db from the 8 db loss predicted in section h.2.1. This deviation can be accounted for in the same way as the clipped sine wave case. The effect of the input impedance variation for the full wave rectifier generator is shown in Fig. 5-7• The curves present the variation of the input level as measured at the input to the full wave circuit for three power levels. The reference levels (dashed curves) were set with a 50 ohm termination. Both of the rectifier diode harmonic generator types constructed produce usable output spectrums through at least I GHz with reasonable agreement with the ideal prediction. Several different diodes or diode pairs were used to obtain the data presented along with interchange of transformers. The diode pairs were matched to less than 10 mv deviation from each other over a current range of 0-30 ma. x Se co nd Ha rm on ic Ou tp ut in db (r ef . P^ n ) 1200 I n p u t f r e q u e n c y i n M H z Fig. 5-5. FULL WAVE HARMONIC GENERATOR OUTPUT. 1 0 7 Se co nd H ar mo ni c ou tp ut in db (r ef . c *r4 CU -5 -10 - 1 5 -20 - 2 5 H IM E U StT CU C2ZR5 aon 1200 I n p u t f r e q u e n c y i n MHz. Fig. 5-6. FULL WAVE HARMONIC GENERATOR OUTPUT. 108 x) C -H C O •r4 4J rl •H H n) > +-» & c H State 200 krr ;fctBBl- 800400 600 F r e q u e n c y i n MHz. Fig. 5-7 INPUT LEVEL VARIATION - FULL WAVE GENERATOR. 1000 1 0 9 H O 5.1.2 BROADBAND SRD GENERATORS. The various curves in the analysis of the broadband. Step Receiving Diode (SRD) generator of Section U.2,3 were obtained by assuming that the diode discontinuity was instantaneous. This is not the case with practical diodes. The actual transition time associated with each diode used is given in Table 5-1, and this finite trans­ ition time will result in an attenuation of the harmonic content. Using a single-pole approximation to account for a 10 to 90 per cent transition time t^, the harmonic frequency at which a 6 db degrada­ tion will occur is f = 0.35/t^ and will continue at approximately 6 db for each octave as higher harmonics are considered. The correction curves of Fig. 5-8 were generated to account for this degradation of the expected output harmonic spectra. A set of curves for multiplier input frequencies of 100, 200, 300, and 400 MHz are presented for the diode transition time of 2.0, 1.0, 0.5, and 0.3 ns. The variation of the minority carrier lifetime (r) due to temperature can be offset by the choice of the diode to be employed. If the tor product is maintained at 10 or greater the effect of the lifetime variation can be minimized (see Fig. 4-25). Several broad-band SRD harmonic generators were constructed as shown in Fig. 5-9. The transformer used was of the type previously discussed and had 4-turn windings. The harmonic spectrum obtained Lo ss Co rr ec ti on in db W w 1 0 0 M H z H a r m o n i c N u m b e r n F i g . 5 - 8 . C O R R E C T I O N C U R V E S F O R S R D M U L T I P L I E R S . 112 V I . Fig. 5-9. BROADBAND SRD GENERATOR CIRCUIT. from the experimental multipliers are presented in Fig. 5-10 through Fig. 5-14 for five different diodes. The various multipliers were driven at a nominal power level of +10 dbm. Measurements were obtained by a test circuit connected as shown in Fig. 5-2. Considering finite diode transition time and transformer losses yields reasonable agreement between the various harmonic specttirms obtained and the theoretical spectra of Section 4.2.3. The diode conduction interval, , of the multiplier varied from approximately 220° for the hp 0112 and hp 0151 diodes to 260° for the hp 0102 and hp 0103 diodes.' This conduction interval measurement was obtained from a sampling oscilloscope waveform. OS C YU 5 Cu 20 4 0 : = — - - - : - : T: : J — —- -H>——-———- - -C - PL Z z ZI _ _ _ -j _ J — U- t Z _ J I I S I I Ioa t < —L r _ ZL _ z-L _ _ _ T73S I I U I S $ Z Ir _ 2C[ 1 _ ZIJC£ £EZ ; - - - - _ 1 Z _ - - _ _ _Z PS _ ———J Z - _ Z — Z_ Z* _ I S r -♦ — 4 Ji Z%♦ I* - CV E ♦n j Z♦, G2 ) uC Lj 4 IC\ Vj r- - r !♦ I L> n I _ _ 3 ,, _ ♦ • rU rJ_ 3 2 5r 5 _ _ _ _| - pV 5 □A ♦4• I L __ If ■- P Z I4 *4 _ J1J I _ - J I 3 _ J ♦ □• ♦ ♦ 5r_M •4 □Z * > p » <♦ - -“ P I*. • M p -fc 5* - P - _ 5 '♦ 1 rWZrZjI I I _ ± ♦, I L - I*' *1 K _ * Z_ It1 p j _ _ Lc I ZH _ LLL _ J _ ] „LJ U _ P F - — r — C LJ_ ICLC I L I — — _ — — — — _ i— _ J LtX = - — _ ”“~“~ PI I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Ij I I I I 500 1000 1500 2000 Output Frequency In MHz Fig. 5-10. BROADBAND SRD GENERATOR OUTPUT. 113 in d b c CU : - :r —~ _ ”j- - -:—- -7---- ---=----- - -- =--- _- ---:-“ ---- = - —_—_ :-- I —- -— -_ - ---- - -- = ---- :---- ----- - ----- I- - -: ------I - ---I- --- ---■i ----- ----- _ - -- - -- I I _ - - - -- - -—- --Z-- -- ------- _- -_ ----- - - -------- _ ------— ------ --=--- - -- ------- - -------- --------------- :--- - -- -- ----- ----- --- -- -----H----- --H---— - -— -— ----— ----- —__- E t' 4- ■ Z - ij J. — —— ——— --- -- ---1■--- - p - : r----- --- -—- - —— Ii 1aF IiI- - -----:III= --- --- -- - f]~— 5 — ---——— —-—— -— --— -— - > 7] - CN 1221* sI- s. t k- 5 ♦Z - 5- _ p 5T U £5Q -j • Zj. V I - _ _ _ i 5 2_ Z v z,_ r 5 L J 5j __ - 5 ** x — > Z C ZI_ 3 Z. __ s; _ > I L _ J ft _ _ U J r"xr_ 1- ^1 _ !» %V _ 5% 5 r:*■ ---——------—_—-——_ 1 J 3 "T !5iS!i!i£2_♦. t [ft v Zi H C 1500 Output Frequency in MHz Fig. 5-11. BROADBAND SRD GENERATOR OUTPUT. H H 2000 Xl •o C M-I ti 6gP -20 -40 3I3E -ET ■ V f i :z». •t r«- v; .5: rt Ti lrL: W* % 4 v 35: N fv 5, S v T 4», U- - ' ' S ti: 5t <■ r"f.i FH 5oo iooo Ijjoo- Output Frequency in MHz Fig. 5-12. BROADBAND SRD GENERATOR OUTPUT. 2000 1 1 5 OJ3 T3 5 -20 5 OL1 - 4 0 % T O -N- 3- 2c IC44K&L ■■4- f 8 4 » - rtiz- -N- Is: dr: Sr: I * r 50 0 1000 O u t p u t F r e q u e n c y i n M H z i -MTrrfft 15000 F i g . 5 - 1 3 . B R O A D B A N D S R D G E N E R A O U T P U T . H H ON 2000 N1000 2000 Output Frequency In MHz Fig. 5-14. BROADBAND SRD GENERATOR OUTPUT. 1 1 7 118 The input impedance of the multipliers tested varied approxi­ mately 2:1 over the input frequency range of 100 to 500 MHz. The external vias voltage, V, vas. at zero volts for the data presented. This voltage was adjusted to optimize various harmonics as the multipliers were in operation. The variation of harmonic amplitudes was consistent with, the expected variation presented in 4.2.3 as the bias voltage V was varied causing the conduction interval, , to change considerably. The various multipliers constructed were operated over a -10° to 50°C temperature range with no apparent degradation in performance. The external bias voltage was held at zero volts for the temperature tests. / 5.1.3 SRD RESONANT LOAD HARMONIC GENERATORS. Several SRD resonant-load harmonic generators were constructed with transformer coupling as shown in Fig. 5-15. The input trans­ former used was of the type previously discussed and had 10-turn windings. The harmonic spectrum obtained from several experimental multipliers are presented in Fig. 5-l6. The fourth order spectrum of Fig. 5-l6(A) was obtained from a multiplier constructed for 200 MHz output using a hp 0102 diode. The multiplier was operated with the bias voltage V at zero volts and the output coupling link 119 I V I Fig. 5-15. RESONMT LOAD SRD HARMONIC GENERATOR CIRCUIT. I terminated in 50 ohms. The circuit values for this multiplier are as follows: L = .OU ph C = l6 pf Q2Zn =- 5 = .25 (for R^ = 50 ohms) Fifth and sixth order multiplier operation produced spectra containing the desired harmonic at -20 db (reference - = 20 dbm) and all other components at -40 db or lower. Fig. 5-l6(B) shows the spectrum obtained from a multiplier using a hp 0103 diode and the following circuit values: L - . 08 yh. 1 . ' C = 32 pf ' Q2Zn = 1.75 ' I SR D Ge ne ra to r Ou tp ut in d b 120 F i g . 5 - 1 6 . S R D G E N E R A T O R O U T P U T W I T H T R A N S F O R M E R I N P U T A N D R E S O N A N T L O A D . 121 The 9th order output was -20 db with, undesired components -ko db or lower. Circuit adjustments were made for operation through the 17th order. Desired outputs of approximately -20 db and undesired outputs of -40 db or lower were obtained. Another multiplier was constructed using a hp OllU diode and a tunable cavity as the output circuit. For a 50 MHz input signal the multiplier could be adjusted for operation at the 15th through 20th harmonic. The spectrum shown in Fig. 5-l6(C) was obtained with the cavity tuned for the l8th harmonic. This spectral distribution was typical for the .range of operation observed. Desired harmonic levels were in the -15 to -20 db range. The transformer input of' the multipliers were replaced with LC impedance matching networks and self biasing circuitry. Typical output spectra obtained with the tuned inputs are shown in Fig. 5-17« The conversion loss obtained for harmonics of n > 9 was typically -n db. Multiplier circuits were operated over the -10° to 50°C temperature range with no apparent degradation of the output harmonic I energy. SR D GE NE RA TO R OU TP UT in d b 122 SESBSSBSOZSB! F i g . 5 - 17 . S R D G E N E R A T O R O U T P U T W I T H ..TUNED I N P U T A N D R E S O N A N T L O A D 123 5.2 DIVISION. . In this section the experimental vork that was performed with. the frequency divider discussed in Section 4.3.1 is presented. Frequency dividers were .designed for subharmonic operation of order 1/2 through the 100 MHz to I GHz frequency range with component placement as given in Fig. 4-36. The frequency ranges used in the experimentation are 100-200 MHz, 200-400 MHz, 350-700 MHz, and I 500-1000 MHz. The values for the inductors L and the capacitor C were calculated using equation (4-10) for = 50 ohms and are tabulated in Table 5-2. I Table 5-2 L M D C VALUES FOR FREQUENCY DIVIDERS U)" (MHz) L(iih) C(pf) O 200 .056 22.6 4oo O ro 00 11.3 6oo .02 8.0 700 .016 6.45 1000 .011 -z 4.5 The experimental test circuit used for measurement of the . divider operation is that of Fig. 5-2 with the divider as the unit ' under test. I2h Fig..5-18 through 5-25 show the operational data obtained from the above design values and the four different step recovery diodes used. Fig. 5-18 and 5-19 present the required power level for the execution of the subharmonic oscillation of order 1/2 and the effect of input impedance variation respectively for the 100-200 MHz divider. The power levels for which the divider will execute a subharmonic oscillation consists of the area between the two threshold curves shown for each diode. Fig. 5-20 and 5-21 present the opera­ tional data for 200-400 MHz divider. The 350-700 MHz divider operation data is presented in Fig. 5-22 and 5-23, and the 500- 1000 MHz divider data is shown in Fig. 5-24 and 5-25. The effect of the diode parameters can be readily seen in Figures 5-18 and 5-20. In each case as a different diode was used the value of the input capacitor C was adjusted slightly to obtain as wide an operational frequency bandwidth as possible.' Proper divider action over the desired range of the 350-700 MHz a n d •500-1000 MHz dividers could be obtained with only the hp 0151 diode. The parameters of the hp 0112 are starting to have their effect on the divider operation as can be seen in Fig. 5-20. The operational power level data obtained for the various experimental dividers, presented in Fig. 5-18, 20, 22, 24, all present the general shape predicted by Fig. 4-45• The data pre­ sented in Fig. 4-45 was calculated for a 500-1000 MHz divider circuit. I n p u t F r e q u e n c y I n M H z Fig. 5-18. DRIVE LEVEL 100-200 MHz DIVIDER, J3 T3 C *r4 § •r4 4-1 nJ-T^ U cd > 4-> a C H -C. -ic- -Z y / X I ^ ^ 8 V # iiTililiiii 100 200 I n p u t F r e q u e n c y i n K H z 300 4 0 a Fig. 5-19. EFFECT OF IMPEDANCE VARIATION 100-200 MHz DIVIDER. 126 E J2 •u CJ I CL, •y a CJ H Fig. 5-20. DRIVE LEVEL 200-400 MHz DIVIDER. 1 2 7 \100 200 300 F r e q u e n c y i n K H z 400 500 Fig. 5-21. EFFECT OF IMPEDANCE VARIATION 200-400 MHz DIVIDER, 128 In pu t Po we r in db m Input Frequency in MHz J Fig. 5-22. DRIVE LEVEL 350-700 MHz DIVIDER 129 Xl -o c •rt •r4 4-> cti •r4 td > 4-> 3 Cu C H I n p u t F r e q u e n c y i n K H z Fig. 5-23. EFFECT OF IMPEDANCE VARIATION 350-700 MHz DIVIDER, 130 •> SXl X ) C •r4 I a 4-1 3a H 10 3 A 1 L - V ’V. L I*t'* v‘ Iv V NV \v % Xr.’-i. r-L* V— *\% «5 \ ♦ • I EV S ♦ X > W♦ X► . V, s> . S # 4 » X S Tft > . 5V p. I \ W H i ynT' ill= ikt 'i?] -Irr % 5: 4.1 TV- 4 y-1 6 0 0 8 0 0 I n p u t F r e q u e n c y i n M H z 1000 Fig. 5-24. DRIVE LEVEL 500-1000 MHz D I V I D E R . 1 3 1 1100 I n p u t F r e q u e n c y i n M H z F i g . 5- 25 . E F F E C T O F I M P E D A N C E V A R I A T I O N 5 0 0 - 1 0 0 0 M H z D I V I D E R , 132 133 Power curves of Fig. $-24 were obtained from an experimental divider designed for this operational frequency range and comparison of these data sets indicates reasonable agreement between the theoretical and experimental data. The junction potential, ip , of the hp 0151 diode used is approximately 0.7 v. In the construction of the individual divider circuits, high Q air coils and good quality variable capacitors were used along with layout minimizing lead lengths and proximity effects. From Fig. 5-19, 21, 23, 25 the input impedance variation can be determined for the individual dividers under circuit operation. The curves present the deviation in db as recorded from the voltmeter (see Fig. 5-2) between the voltage level across 50 ohms and the voltage level applied to the divider input terminals. Several operational output waveforms and 1/2'order harmonic spectrums for the 500-1000 MHz, 200-400 and 100-200 dividers using the 0151 diode are shown in Figures 5-26 through 5-30. These output waveforms are of the general form obtained from the computer analysis presented in Fig. 4-43. The operational waveforms show that, as a function of input power level, the divider may operate with one conducting■and one nonconducting interval or two sets of conduction and nonconduction as was predicted from the computer analysis and presented in Fig. 4-39, 4l and 42. 134 1/2. / 0 / . o , 5 3 » ------ 4 »*£> • So r i>0 a) S p e c t r u m : 2 0 0 M H z / cm; 1 . 0 = 2 0 d b m b) W a v e f o r m : l O O m v / c m ; 2 n s / c m F i g . 5- 26 . O U T P U T S P E C T R U M A N D W A V E F O R M 5 0 0 - 1 0 0 0 M H z D I V I D E R f i n = 5 2 0 M H z ( P in = 20 dbm). 135 10 d b ma) S p e c t r u m ; 2 0 0 M H z / c m ; 1.0 b) W a v e f o r m ; 5 0 m v / c m ; 2 n s / c m F i g. 5 - 27 . O U T P U T S P E C T R U M A N D W A V E F O R M 500-1000 MHz DIVIDER f in = 750 MHz (Pin = 10 d b m ) . 136 a) S p e c t r u m * 2 0 0 M H z / cm; 1.0 = 11 d b m b) W a v e f o r m * 50 m v / c m ; I n s / c m F i g . 5 - 28 . O U T P U T S P E C T R U M A N D W A V E F O R M 500-1000 MHz DIVIDER fin = 1000 MHz (Ptn = 11 d b m ) . 137 a) S p e c t r u m : 2 0 0 M H z / cm; 1 .0 = 10 d b m b) W a v e f o r m : l O O m v / c m ; 2 n s / c m F i g . 5- 29 . O U T P U T S P E C T R U M A N D W A V E F O R M 200-400 MHz DIVIDER f in = 300 MHz (Pin = 10 d b m ) . 138 o i.i Ta .Si 'V ,1 I /o 30 C#o a) S p e c t r u m 5 2 0 0 M H z / c m ; 1.0 = 17 d b m b) W a v e f o r m : l O O m v / c m j 2 n s / c m F i g . 5- 30 . O U T P U T S P E C T R U M A N D W A V E F O R M 100-200 MHz DIVIDER f in = 150 MHz (Pin = 17 dbm). 139 ■ When the input power level to the divider is varied between the operational thresholds the 1/2 subharmonic content ranges from -6 to -l4 db which is a reasonable power level variation. The various spectrum plots of Figures 5-26 to 5-30 indicate that a usable m /2 harmonic spectrum, for m > I, is also available. It appears that this spectrum follows the output predicted for the broadband step recovery diode multiplier. In order to determine this analytically, the solution of the system of equations defining ' the divider operation are required. This has not been done. The various dividers constructed were operated over a 0° to 50°C temperature range with no apparent degradation in performance. 5.3 TRANSLATION. In this section the experimental work that was performed using the ring modulator discussed in Section 3.2.U is presented. The modulators were designed to operate over as large a frequency range as possible, and are schematically represented as shown in Fig. 5-31. The balanced transformers used in the modulator were equivalent to those discussed in Section 5.2. Various diode quads, were chosen to have dc characteristics which were matched to less than 10 my deviation from each other oyer a current range of 0-30 ma. Conversion loss characteristics for two different sets of transformer windings are given in Fig. 5-32 and Fig. 5-33. D 2- Port Fig. 5-31. RING MODULATOR CIRCUIT. The 10-turn transformer had its trifilar winding equally spaced around the periphery of a toroid core. The 3-turn transformer windings were laid in as close as possible to each other. Each of the sets of characteristics are the averages of data taken for several different transformers and several different diode quads. For the data presented the translating (switching) signal was applied to port 2 at +7 dbm and the signal to he translated applied to port I. Power levels of -10 dbm and -20 dbm were used as the drive level at port I. From Fig. 5-32, 33 it can he seen that the modulator with 10-turn transformers yield superior performance over the lower frequency range of 10 to UOO MHz, whereas, for the frequency range extending on up to I GHz the modulator with, fewer turns provides more acceptable performance' characteristics, •\ H -E- H Fig. 5-32. FULL LATTICE MODULATOR CONVERSION LOSS. IE K ic aE a a is e r iaB flB is iiR ii B/]5HE™n35S555! 2 0 0 4 0 0 6 0 0 S w i t c h i n g F r e q u e n c y i n M H z ( P o r t 2) 1000 Fig. 5-33. FULL LATTICE MODULATOR CONVERSION LOSS. Ih2 The carrier .rejection curves of Fig. 5-3^ indicate the relative balance presented to the circuit by the transformers and diodes quads. The carrier rejection labeled "forward" was measured across a 50 ohm load at port 3 with, port 2 terminated in 50 ohm and a drive signal of +7 dbm at port I. The reverse rejection was measured with port I and 3 interchanged. The rejection presented by the modulators using 3-turn transformers is much more acceptable than the 10-turn transformer modulators. This is as expected since the matching' of lead lengths and uniformity of winding spacing between turns is easier to control. From Fig. 5-35 the effect of the input impedance variation of the modulator is shown. The curves present the deviation in db as recorded from a voltmeter (see Fig. 5-2) between the voltage level across 50 ohms and the voltage level applied to port I with ports 2 and 3 terminated in 50 ohms. Typical impedance characteristics (R^, X^3 Z) for the two transformers used are presented in Fig. 5-36. The data-was obtained from rf bridge measurements with the transformer center tap grounded and a load of 200 ohms across the secondary windings. The mixer balance from port I to port 3'is relatively the same as the forward rejection to port 3. Port 3 to port 2 is typically 5-10 db less than the reverse rejection measured at port I. The balance measured from port 2 to port I is typically 5 db less than Taoo4 0 0 I n p u t F r e q u e n c y i n M H z Fig. 5-34. FULL LATTICE CARRIER REJECTION. In pu t Va ri at io n in db A 2 0 0 4 0 0 6 0 0 8 0 0 F r e q u e n c y i n M H z 5-35. EFFECT OF FULL LATTICE INPUT IMPEDANCE VARIATION 1000 OCO I G •r4 a x CO G •r4 to n a F r e q u e n c y I n M H z F i g . 5- 36 . B A L Al'] C E D T R A N S F O R M E R D A T A . IhG the forward rejection. The balance from port 2 to port 3 is approxi­ mately 10 db less than the reverse rejection. The mixer intermodulation products are typically less than k5 db (referred to switching level of port 2) under the drive conditions for which data has been presented. These mixers have been operated over the temperature range of 0° to 50°C with no apparent degradation in performance. 6.0 SUMMARY M D CONCLUSIONS In the preceding chapters it has been demonstrated that effective use can be made of several recently developed semiconductor diodes' in vide-band techniques for the synthesis of precision frequencies over vide frequency ranges at VHF and UFH frequencies. The application of these devices vas examined in detail under the operating con­ ditions associated with frequency-translation, multiplication and division. 6.1 SUMMARY OF RESULTS. < ■ As a result of this research effort the performance level of the various signal operations investigated can be reasonably anticipated. The diode harmonic generator constructed produced usable outputs beyond I GHz within 8 db of the predicted values. Both of these circuits have applications where frequency doubling is desired. The performance of broadband SRD multipliers with resistive loads can be predicted by using the conversion curves of Fig. h-25 and the diode transition curves of Fig. 5-8. In applications requiring harmonics of the third to the sixth, a diode can be selected that will provide usable output levels. Holding the bias voltage of the diode at zero volts will not seriously degrade the multiplier performance while eliminating any temperature dependence of the output on the biasing circuitry. Ik9 The output of a broadband SRD generator with a resonant load can be predicted by using the curves of Fig. U-3U or Fig. 4-35 and Fig. 5-8. To use these curves circuit Q's must be Imown or estimated. The spectral output of this multiplier peaks at the desired harmonic with a better conversion efficiency than that of the resistive load generator. .However, the frequency range of operation is limited by the resonant-load characteristics. The realization of a broadband divider circuit can be obtained from the calculated values for the various circuit elements'given by the relationship of equations (4-10). . Proper subharmonic spectrum generation of the order 1/2 was obtained through I GHz employing the hp 0151 diode. Other diodes used were useful over various frequency ranges depending upon their capacitance, minority carrier lifetime and transition time. The hp 0151 diode had the smallest values for all three of the above mentioned parameters. The dividers tested generated a m / 2 spectrum which appears to follow the broadband SRD generator characteristics. The various circuits discussed above all have outputs that contain a number of other harmonics along with the desired one. Additional filtering must be provided in applications where the output must contain a single frequency. If the various analyses are to be used, the additional bandpass circuitry must be isolated from the circuit outputs under discussion by either an amplifier with a 150 resistive input impedance or by a resistive attenuator. A voltage- tunable .narrow-baod filter could be used in applications where filtering is required over a certain frequency range. Ring modulators to perform the frequency translation function can be implemented using carefully constructed trifilar transformers and matched diode quads that have a very broad operating frequency range. The 10-turn transformer configuration provides an operational frequency range of 10 to 400 MHz- and the 3-turn configuration has a usable range extending to I GHz. Carrier rejection of -30 db can be maintained with a conversion loss of 5-10 db for switching levels of +7 dbm and drive levels of -20 to -10 dbm. 6.2 SUGGESTIONS FOR FURTHER RESEARCH. It is suggested that further analysis be done in the following J areas: (1) Further analysis associated with the prediction of the 1/2 ' order harmonic spectrum energy of the frequency division technique discussed is recommended. • (2) To date, the analysis of the step recovery diode circuit operation has been, limited to fixed bias operation. It is suggested that an investigation of allowing the bias to be varied by a low frequency signal be undertaken. With further investigation it might be possible to employ this technique 151 to produce phase control over the output signal. A P P E N D I X 41. APPENDIX A DERIVATION OF SHORT-TERM FREQUENCY STABILITY In this section a relationship between short-term frequency stability of a signal and the signal-to-noise ratio is presented which can be used in determing the effects of signal operations on the basic stability of an oscillator system by considering the degradation of the signal-to-noise ratio. The analysis presented here can be obtained from references [2l] and [22]. Short-term frequency stability is expressed as the ratio of the rms frequency deviation in the measuring interval R to the nominal frequency of operation, where the frequency deviation is due to random noise effects. Long-term effects of aging and temperature changes along with initial startup transient effects are not con­ sidered. For this discussion the output signal characteristics of the signal source (oscillator) are of interest and- not the oscillator model which would present the mechanisms which produce the output .signal and noise. The noise effects in the output of a signal source are classified into two types. Type I noise is considered to be generated within the oscillator. A noise pulse within causes a permanent phase change that cannot be corrected. Type I noise effects cause a cumulative phase error as additional pulses appear. Type II noise includes the noise which is external to the basic oscillator and does not have an effect on the basic oscillator. =Type II noise results in a phase error which is not cumulative. The effects of Type II noise are only instantaneous. Therefore, Type I is classed as an infinite memory and Type II is zero memory. Consider the oscillator signal designated as s (t) = A cos to t (A-l) with the noise expressed as v (t) = v cos to t + v sin to t (A-2) n c o s o where- to is the midhand angular frequency and v and v are O C o uncorrelated functions of time which vary slowly and randomly as narrow-hand'random processes. The signal of interest is expressed as V1Ct) = s(t) + vn (t) = (v +A)I cos to t + v sin to t. (A-3) C O S O An equivalent form for (A-3) is expressed as V1Ct) = p (t) cos [ w t + (t)] (A-U) where p^(t) = [v + A]^ + (A-5) - tan (t) = ' - ^A-6) C The function p(t) is called the envelope of the wave and 9(t) is called the phase of the wave. With large signal-to-noise 155 ratios (t) = vg/A (A-7) From (A-7) the cumulative phase error due to Type I noise for k pulses in the measuring time r is given as [V1 V V 2 ^ V1 IZA (A-8) The number of independent noise pulses from the sampling theorem is k = 2W., T (A-9) . P 1 ' where is the single-sided bandwidth of the noise. Since the phase error due to Type II noise pulses is not cumulative, the error due to this type of noise in the measuring interval is expressed as ~ 31wY ZF1wu Z* wPF"WZ The total phase error is expressed as n SW1T T) pr2 V l + ^ (A-l8) ■ y YX and the fractional frequency stability is (atoT)2 1/2 _ W1H1 - "2 ,1/2 O O - (A-19) The signal-to-noise ratio for the noise can be expressed as ' (SHB)1 = § I (SHfi)2 = £ ^ Using (A-20) in (A-19) yields s „ L r " l + - I ] l / 2 T ~ “o (SBB)2T2 J (A-20) (A-21) Equation (A-21) is the principal result of this Appendix and shows the importance of both types of noise power, the Type I "bandwidth, and the measuring interval. APPENDIX B NONLINEAR DEVICE ANALYSIS. In this discussion the output relationship for a general non­ linear device is determined from analyses presented in references [22] and [23]. The input-output relationship for the general non-linear device is given "by Vo = J1Vin 3 where n j is the output function. v. = (A + V ) cos to t + v in c o s (B-I) Assume an input to the device of sin w^t (B-2) where v cos oj t + V sin w t is narrow-band noise of center frequency C O s o . f . The mk*1 term of (B-l) will yield the following terms of interest v. 131 = (A+v )in cos™" um t + mv (A+v )m cos™" "^cot sin co t. (B-3) in c o s c o o With large signal-to-noise ratios at the input, to the device only the linear noise terms will be of importance and (B-3) becomes v. m = [Am+inAm "^ v ] cos™ Z5 t . +.mAm cosm "*"aj t sin Z5 t . (B-H) in c o s o o - After appropriate trigonometric substitutions and manipulation, the signals in V m at the harmonic of the input frequency (for k = m-2p) are 159 (V. f = [Am + mAm-1v ] 21“m .( ) cos a t i n k ^ 1 - nf-Cm-k)' -i, -i -UJ- + 21“m kAm-1v (n ) sin k w t , 3 — (m-k) (B-5) vhere ( ) or C denote the binomial coefficient, r n r Using the above relationships the output power at the desired k 1"*1 harmonic is D % (§)2P (% + ZP)a% + ZpT p=0 i (B-6) how, if the condition + 2P .+_1 [(k + 2p + 2)] (k + 2p)-1« I k + 2p p+1 (B-T) where in 2 then (B-6) can be approximated as pO = 2l~ \ n \a, [I + (k+2) P,.„ '- I + -- Iin a. (B-8) If the condiiton of (B-T) holds the noise output power becomes %0 = 2 ^^ kP. k"1W.k2a12 [l +i k (k+2)(k+1) " k+2 1 k in a. (B-9) l6o The output' signal-to-noise ratio "becomes (SNR). (SNR) [I - k a, i M (k+2) 3S±2 p i (B-IO) thus, if ak + 2p, for some p > 0, is not zero the. (SNR) < (SNR). (B-Il) and. the'^h law device, with m > k, will yield a lower signal-to- noise ratio and therefore a decreased signal stability. i APPENDIX C • CALCULATION OF THE HARMONIC SPECTRUM OF A CLIPPED SINE WAVE A/WxA--------£>j ■ R D S V . JL • Fig. C-I. HARMONIC GENERATOR EQUIVALENT CIRCUIT. Assuming the input voltage to he V^ cos wt the resulting output voltage across R for the interval -Tr£iot 0 (C-I) The output waveform.is shown in Fig. C-2. V /(R + Rt) C-2. OUTPUT WAVEFORM FOR HARMONIC ANALYSIS OF THE CLIPPED SINE WAVE. The output voltage, being an even function of time is represen­ table by a cosine series. The normalized Fourier coefficients of cos nMt are 162 a = — n lY (cos tot - cos 8) cos mot dtot -6 I I r sin(n-l)6 sin(n+1)6 2 sin n8 cos 8 (n-l) n+1 ' th The conversion loss in. db at the n harmonic is defined "by PL - 10 Io ^ower available from'generator n g Power output at harmonic (C-2) (C-3) For the assumed input voltage, the available power at the input is „ 2 in 8R ’ (C-4) The output power at the n harmonic is V 2 a 2 R 3 = _m___2___ * 2(R + R^)2 (C-5) Substituting (C-U) into (C-3), the conversion loss for the n harmonic is th yYlnY = -10 log a 2 for R = R,' (in db). (C-6) LR n g L The computer programs used to calculated the conversion loss as a function of 8 can be found in the. computer program Appendix. APPENDIX D NONLINEAR CAPACITOR ANALYSIS V cos art m A/WV R S NC V R L Fig. D-I. NONLINEAR CAPACITOR EQUIVALENT CIRCUIT. Assuming the input voltage to he V cos wt, the resulting output voltage across RY for the interval -0 isL — — v(t) = (cos tot - cos 0) -8 = 0 <(ot<2ir~d (D-l) The output waveform is shown in Fig. D-2. tot' = -0 tot = 0 Fig. D-2. OUTPUT WAVEFORM FOR NONLINEAR CAPACITOR ANALYSIS. When the net voltage across the nonlinear capacitor is in the forward direction, the capacitance for this state is very large. Since the capacitance is large, the current amplitude is determined "by R and R . When the applied voltage is reversed, all the charge L g which was stored during the forward bias interval will be recovered. Referring to Fig. D-2, this requires area A^ = A^. When tot = - for corresponding specific values of 0. Numerical values for may be obtained from Fig. D-3. The normalized Fourier coefficients of the expansion of (D-l) for n f I are given by I p sin(n-l)^ sin(n+l)4 _ cos 8 sin n^ an TT 2(n-l) 2 (n+1) - n sin(n-l)0 , sin(n+l)0 cos 8 sin n8 + “ 2(n-l) . 2(n+1) " n J , _ I r cos(h—I )(f) ' cos(n+l)(j) cos 0 cos n^ bn “ 7 L“ 2(n-l) 2(n+1). n ■ ; cos(n-l)8 , cos(n+1)0 cos 6 cos n0 n m ^ + ~2{n-iT ■ 2(n+1) ■ n J ^ \© i n d e g r e e s F i g . D - 3 ^ a n d © F O R N O N L I N E A R C A P A C I T O R A N A L Y S I S . 166 Here and are the coefficients of cos nut and sin nut respectively. The output power at the n - harmonic is Pn = -vA 7 SA 0 ( - 2 K 2 9)8t* The conversion loss for the n harmonic is (for R = R ) _m g PLn = -10 log (an2 + bn2 ) (in db). (D-7) The computer program used to calculate the conversion loss as a function of 0 and can be found in the computer program appendix. ■ APPENDIX E STEP RECOVERY DIODE ANALYSIS' Fig. E-I. STEP RECOVERY DIODE GENERATOR EQUIVALENT CIRCUIT. Assuming the input voltage to be V^ sin wt the resulting output voltage across R^ for the interval -8 is v(t) = V^ [sin(u)t + 8) - sin 0] '8 : \ 6 ---- (j,------> / K . y _ V = V /(R + m m g Fig. E-2. OUTPUT WAVEFORM FOR STEP RECOVERY DIODE CIRCUIT. The steady-state condition for 6 and the charge (Q) is zero, substituting this condition into (E-U) gives the solution for 0 in terms of ruY and as zt COT Tan 0 sin - uncos cj) + coTe FruY sin + ruXYX (l-e ^ ) + % (E-5) The computer programs used to calculate 0 as a function of and ruY can be found in the computer program appendix. The normalized Fourier coefficients of the expansion of (E-l) are given by I 2 a1 = [sin (0 + cj)) - sin 0] for n f I I r cos(n-l) (0+cj)) - cos(n-l)0 cos(n+l) (0+tj>)-cos(n+l)0 an - 2Yt b (n-1) (n+1 ) -2 sin 0 sin n (0+^) - sin 0 sin n0 i6p I ' I ^ 2Yt [0 - 2" sin 2 (0+^) + 2sin 0 cos (6+) - sin 0 cos 6] for n ^ I d- = L- r sin (n-1) (8+4)) - sin (n-l)0 n 2lY L 7 ' (n-1) sin (n+l) (9+4)) - sin (n+l)6 (n+1) , 0 sin 0 cos n(e+) - sin 0 cos n0 ^ — ---------- J Here and are the coefficients of cos nwt and" sin ncut respectively. (E-6) The output power at the n harmonic is Vm2 BL (an2^ n2) 2wf 5vl)2 (E-7) "til. The conversion loss for the n harmonic is (for RY N R Z L g' PLn = -10 log (an2+t>n2 ) (in db). (E-8) The computer program used to calculate the conversion loss as a function of tox, 0, and 4) can be found in the computer program appendix. Values used in the calculation for tox, 6, and were generated using the computer program for equation (E-5). For the discussion that follows the'load resistance R^ in the circuit of Fig. E-I is replaced by a resonant circuit R LC. The harmonic power generation of this circuit is restricted to the following operation. When the applied voltage across the diode is 170 positive, diode conduction starts and current flows in the circuit until the charge that has passed through the diode becomes zero. At this time the diode switches off leaving the current "j flowing in the inductance. The stored energy is dissipated in the load before the beginning of the start of the next conduction period. The results of the analysis will be the determination of the harmonic generating efficiency. The analysis considers two conversion losses and the overall total loss being the sum of two quantities. The equivalent circuits associated with this manner of operation are shown in Fig. E-3 for the conducting and nonconducting states. Fig. E-3. HARMONIC GENERATOR TOTH RESONANT LOAD EQUIVALENT CIRCUIT. (a) Conducting equivalent circuit. (b) Nonconducting equivalent circuit. • 4 The conducting state will be analyzed first. For convenience let V = kA. The circuit driving voltage v(t) is expressed as 171 v(t) = A [sin (wt - 8) + k] (E-9) Vnere t is measured from the beginning of the conduction state. For the circuit of Fig. E-3a, using the initial condition of i = o at t = o, the circuit current is expressed as sin 0 + Q cos6 p +/T 1 ] e"RSt/Li^ = — [sin 0 + [-sin 0 + I + Q.I sin (cot - 0) - Q cos (cot - 0) + ------------------L 5------------ ] I + Qn (E-IO) Equation (E-IO) can also he expressed as i = L - [sin e * sln^ t * [-sin 6 * SlS-tilti ] g e-Egt/L) (I i Q12)178 (IiQ12)172' (E-Il) "where ' Q.I R and , ' , coL tan = — . g (E-12) The charge (q) that has passed through the diode is expressed as ft . i. dt. d (E-13) From equation (E-13) the charge (q) is expressed as 172 A r, . Q COS (tit - d - lp) - COS (6+lJj) g = \ [t S l n e ------- ^ ¥ 7 2 ------- --- - j f [=in e - ^-^-94 W ) (I - e - V /L)] Bg (I I- Q12Iiz2 (E-Iit) If iot = cf) when q = o, the diode ceases conduction and a relationship in terms of conduction constants 0 and and the circuit parameter Q1 is given "by- tan 0 I - cos cf) - Q1 sin * + (l - e ^ l ) Q1-Q1 cos cf) + sin cf) - (l+Q^cf. + Qj3 (l - e_ is 2 2 , I T T 2 ' I 'LA I . n J = - L I = v - --- p- joules. ^ R (E-17) 173 The total harmonic power associated with (E-IJ) is expressed as 2 2 oiLA I U YYR 2 g watts; (E-18) A conversion loss can now be defined associated with the conduction interval as r Available Power 10 log L ------ ---------- J where p Power Available = A /8 R for V < o. g Substituting into (E-19), the conversion loss becomes (E-19) ykl N 10 log ( — ) db. ZQ1I (3-20) Jtfumerical data for P was obtained using equations (E-15) and (E-l6) assuming values for )/w and T = 2YY6S H From (E-23) TpLw Qz. v = n (— J-j Im )(*-£) *2 r _-n(n-*/2)/Q; , -1+e- W2 2Tm .Ll"e 2 + ” I + j4Q2 ] (E-24) Now provided that most of the power from the damped oscillation has been dissipated when it is terminated by the start of the next conduction interval, the exact point at which the waveform terminates is immaterial. Therefore, suppose that 4n(Tr-ij)/12) is a multiple of 2IT and provided 4Q^ » I, the last term in the brackets can be neglected in comparison to unity. With these approximations 175 v is expressed as vn s - ^ T - [l- ^ n/S2 (I- - f/S)]. (E-25) The second conversion loss P can he defined as ^ "*"°® ^ Power at nu in KY (E-26) Therefore, P can he expressed as PL2 = 10 log ^ ] dh 1.961 - 10 log [ — '(1-e n 7^r */2) /Q2].. (E-27) Numerical data was obtained assuming values for and Q^/n hy the digital computer. The program used in the computation is given in the computer program appendix. For a given conduction characteristic , the total conversion loss in generating the harmonic mo is found hy adding P and P 0 L-L Ld calculated from the appropriate circuit constants. It was assumed in the analysis that the energy was all dissi­ pated during the nonconducting state. A limit of one tenth of the initial energy left at the next conduction starting, was determined experimentally [17] • The analysis also ignored the effects due to ■ the capacitor during the conduction state. It can he shown hy appropriate computation that for operational "condition removed from . the maximum inductive energy condition that this approximation is 2 reasonable and improves at the rate of n . Therefore its effect on the conduction characteristic "will be small. APPEITOIX F STEP RECOVERY DIODE FREQUENCY DIVIDER ANALYSIS In this discussion the ideal nonlinear capacitor character­ istics will he assumed for the step recovery diode. This is justified for ruY > 10 as was presented in Chapter 4. The analog simulation of the circuit shown in Fig. F-I will he considered first, as it will he used as a subportion of the overall analog simulation of the divider circuit. The circuit consists of an ac. generator, v(t), in series with a bias source, Vq , driving the SRD diode and the resistive load,, RY . The diode' starts to conduct when the voltage across it is zero and continues in the Fig. F-I. SERIES STEP RECOVERY DIODE AND RESISTANCE EQUIVALENT SRD CIRCUIT. 178 conduction state until the net charge that has passed through it is zero.. The diode stops conducting when the charge that has passed through it is zero and remains nonconducting until the voltage across it again becomes zero. The analog simulation of this circuit is given in Fig. F-2. Fig. F-3 presents the input output relationships for the simulated circuit for a value of + Y - -.5v. The simulation presented is actually for a negative v(t) in with the output of amplifier 47 providing v(t) - (\p + V ) . These polarities are required in the overall simulation that follows for the complete divider. v(t) - (> + V) —v (t ) -£— 1N2 . if- Comparator Fig. F-2. BLOCK DIAGRAM OF STEP RECOVERY DIODE IN SERIES WITH R SIMULATION. 179 F i g . F - 3 S I M U L A T E D D I O D E C H A R A C T E R I S T I C S . Fig. F-U. SRD DIVIDER EQUIVALENT CIRCUIT FOR SIMULATION. The equivalent circuit of the divider is shown in Fig. F-U. The node analysis of this circuit, yields the following set of equations: (Ti-Y2 ) C1 (T2-T3 ) wYcFYT' H " R L. v^dt + - (v3 - V^) dt Cv3-Vu) dt CgV^ + id. (F-I)' I L l8l ■Rearranging (F-l) gives V2 T1 R C ^2 + ^3_ 6-1 ESC1 V2 L .R v at + J Ii vIidt V, ■ I -Jt I T3a t - LCr Tltat " 5^ (F-2) The values to he used for simulation are Rl = 50 R = 50 S L = .012yh C1 = U.5pf Cg = 2.Opf (assumed stray capacity). Using these values and time scaling T = IO10 t equations (F-2) become v^ = v| - .444vg + .bbhv^ V^ = Vg - .833 v^dt + .4l7 vUdt v^ = .417 Vgdt ~ .4l7 V t ‘ 50 ^a (F-3) Equations (F-3) were used in the analog simulation of the divider. The block diagram and computer connection scheme is presented in Fig. F-5 • :: 182 .444 0- F- e 4 4 4 + I O v ^ 0 9 v^ generator .833 ■15. % + ? C O +1UV - Com p c -||. -L± (Xu INI T IN2 4 $ *ij— Comp, 15 .5 Fig. F-5 BLOCK DIAGRAM OF BROADBAND DIVIDER SIMULATION, APPENDIX G BALANCED MODULATOR ANALYSIS v(t) v(t)f(t) ■ Fig. G-I. DOUBLE BALANCED RING MODULATOR. A switching function, f(t), as represented in Fig. G-2 is assumed to calculate the minimum conversion loss of the type of modulator shown in Fig. G-I with ideal rectifier diodes. Fig. G-2. SWITCHING FUNCTION f(t) The Fourier series for f(t) is J, ' I • f (t) = — [sin 03gt + — sin 3w^t + . .. ] , where h = — for n odd. n Trn (G-I) 184 For an input of v(t) = A sin (o_t the output, = v(t) f (t), is expressed as ■ ' '4A O TT sin 3 to t [sin Ui t sin w t + sin to t ---- -— — sin 5 (o t + sin w t ---- ----- + . . . ] o 5 (G-2) . cos (to -to )t ,cos (to +to )t COS (3m -Ui )t + A r s o s o , s o_ [ 2----------2--- + ---- S--- cos . (3to +to )t -------6^ ~ + (G-3) The amplitude of the sum and difference frequency terms, to -to and to +to , are the only coefficients pertinent to the s o s o conversion loss calculation. The conversion loss (in dh) at either the sum or difference frequency is given by Q g v 7. loZ j m N = 20 106 1 = 3 -?2 ab- (G-h) ■ APPENDIX H DIGITAL COMPUTER PROGRAM LISTINGS C CLIPPED SINE WAVE ANALYSIS X=50.0*3.l4l6/l80.0 DO 40 MM=I,40 M=I PRINT 100 100 FORMAT(1H1,32H FOURIER COEF. CLIPPED SINE WAVE) PRINT 101,X 101 FORMAT(!HO,3X,38 X=,RX3FlO.6) t PRINT 102 '102 FORMAT(!HO,3X,38 N,8X,3H V N ) AX=2.0*X All=(X+( (SINF(AX) )'/2.0)-( (SINF(X) )*(COSF(X) )*2.0))/3.l4l6 PRINT 104,M 3All 104 F0RMAT(1H 35X,13,3X,E10.U) DO 20 N=2,20 Bl=N-I ' B2=N+1 B3=N BlX=Bl*X B2X=B2*X B3X=B3*X 186' Al=(SINF(BI))/Bi . A2=(SINF(B2X))/B2 A3(2.0*((SIBF(23X))*(COSFC X ))))/B3 AN=(A1+A2-A3)/3.l4l6 PVk NP%G,wPVZ ANDB=20.0* CO.43429)*(LOGF(ANL)) PRINT 103,N,AN,INDB 103 FORMAT(1H ,5X,13,3X,E10.4,3X,F10.4) 20 CONTINUE X=X+(I.0*3.l4l6)/180.0 40 CONTINUE CALL EXIT END C NONLINEAR CAPACITOR ANALYSIS 10 READ I, THETA, PHI,I I F0RMAT(2F10.4,13) PRINT 100 100 FORMAT(1H1,3X,28H NONLINEAR CAP FOURIER COEF. ) PRINT 10 101 FORMAT(1H0,3X,2H N,8X,3H VN) M=I X=THETA*3.1416/180.O Y=PHI*3.l4l6/l8.0 187 X2=2.0*X Y2=2.0*Y All=(O .5*Y)+(0.25*SINF(Y2))-(COSF(X)wSIHF(Y)) A12=(0.5*X)+(0 .25*SIHF CX2))-(COSF(X)wSINF(X)) Al=(A11+A12)/3.1416 B H = - (0.25*C0SF-Y2)) + (COSF (X) wCOSF (Y)) B12=-(COSF(X)wCOSF CX)) + (0.2 5wCOSF(X2)) Bl=(Bll+B12)/3.l4l6 AB=(AlwAl)+(BlwBl) ,l NG/Rt,wP%Z ,LA%NcEHES wEHUTUcaZS w^Ez,w,LZZ PRINT 105,MsFl,FlDB 105 FOSMATdH ,3X,12,4X,E10.4,3X,F10.4) DO 4-0 N=2,25 B=N-I BB=N+1 BBB=N XB=XwB XBB=XwBB XBBB=XwBBB YB=YwB YBB=YwBB YBBB=YwBBB 188 ANl=((SINF(YB))+(SINF(XB)))/(2.0*B) M 2 = ((SHF(YBB) )+(SINF(XBB)_))/(2.0*BB) M 3 = - ( ( COSF(X)*2INF (.YBBB))+'(COSF(X)*SINF(XBBB)))/BBB M = ( M 1 + M 2 + M 3 ) /3. ±kl6 BNl=(-(COSF(YB))+(C0SF(XB)))/2.0*B) BN2=(-(C0SF(YBB))+(C0SF(XBB)))/(2.0«BB) BN3=((COSF(X)*C0SF(YBBB))-(COSF(X)xCOSF(XBBB)))/BBB BN=(BN1+BN2+BN3)/3.l4l6 ABN= (M xA N )+(BNxBN) t FN=SQRTF(ABN) FNDB=20.Ox (0.43429)*(LOGF(FN)) PRINT 106,NsF N 3FNDB 106 FORMAT(IH ,3X,12,4X,E1.0.4,3X,F10.4 ) 40 CONTINUE IF(I) 10,10,300 300 CALL EXIT END _ C THETA AND PHI FCNS OF WT= 1.0, TO 1,000,000 WlT=I.0 DO 10 1=1,7 PRINT 100, WlT 100 FORMAT(1H1,3X,5H WT =,2X,E10.4) PRINT 101 189 101 FORMAT(M O , 2X,to PHI,6X,6H THETA) - X=5.0*3.lto6/i8o.O DO 20 N=I,72 XW— X/W1T VH=SINF(X)-WlTwCOSF(X)+WlT‘x‘(.2.71828**(XW)) VD=-W1T*SINFCX)-COSF(X)- W 1 T * W * ( 2 .71828**(XW))+¥lT*WlT+l.O V=VN/VD THETA=ATANF(V) Xl=XtoSO.0/3.ito6 THETl=THETAtoSO .0/3.lto6 PRINT I02,X ,THETA,Xl,THETl 102 FORMAT(2E10.H ,2E10.U ) PUNCH 103, X,THETA 103 FORMAT(2E10.b) x=x+5.o*3.ito6/i8o.o 20 CONTINUE Y=I WlT=IO.0**Y 10 CONTINUE CALL EXIT END 190 C THETA AND PHI FCNS OF WT= .1, .3, 3 . WlT=0.1 DO 10 1=1,3 PRINT 100, WlT 100 FORMAT(1H1,3X,5H WT =,2X,E10.U) PRINT 101 101 FORMAT'(!HO,2X,to PHI,6X,6v tOKtPZ X=5.0*3 .,1H16/180.0 DO 20 N=I,72 XW=-X/W1T VN=SINF(X)-WlTx-COSF(X)+WIT*(2.7l828-x'«( M ) ) VD=-W1T*SINF(X)+COSF(X )-WlTxWlT*(2.71828**(XW)) WlTxWlT+!.O V=VN/VD THETA=ATANF(V ) Xl=X*l80.0/3.lUl6 Y v f Y l NY v f Y g CUO yO"Ci>•iv THETA) PRINT 103,PHI5THETA5PHI1,THETl 103 FORMAT(2E10.h,2F10.4) PRINT 125 125 FORMAT(1H0,3X52H N 58X,3H VN) X=PHI+THETA Y=2.0*X I192 ■ VAl= (SINF (X ) -SINF (TIIETA)) * (S H F (X) -SINF (THETA)) /6.2832 VBl=(PHI-(SIEF(Y)/2.0)+2.0-x-(SII'rF(THETAKCOSF(X))) VB2=-SHF (THETA)-xCOSF (THETA) VBS=(VB1+VB2)/6.2832 ■ ■ VAB=(VAlxVAl)+(VBSxVBS) Vll-SQRTF(VAB) V11DB=20. OxO . 1*3^29XL0GF (Vll) PRINT 111,Vll,VllDB . Ill FORMAT(!HO,3X,28 1 ,5X,ElO.U ,SX,FlO.4) DO 50 N=2,20 A=N TN=THETAxA TNl=THETAx (A+l.O ) TN2=THETAX (A-I.O ) PTN=XxA PTNl=Xx(A+l.O ) PTN2=Xx (A-I.O ) j Al=(COSF(PTN2)-COSF(TN2))/(A-I.O ) A2=(COSF(PTNl)+COSF(TNI))/(A+l.O ) AS=-S.Ox (SINF(THETA)xSINF(PTN)-SINF(THETA)xSINF(TN))/A . \ : AN=(A1+A2+A3)/6=2832 BI= (SINF (PTN2)-SINF (TN2)) / (A-l. O ) : B2=-(SINF(PTNl) SINF(TNl))/(A+l.O ) ! i| 193 B3=2.0*(SINF(THETA)*C0SF(PTN)-SINF(THETA)wCOSF(TN))/A BN=(B1+B2+B3)/6=2832 V=(ANwAN)+(BNwBN) CN=SQBTF(V) CNDB=20.0W0.43429*LOGF(CN) PRINT IlO5N 5CN,CNDB H O FORMAT(IH 53X, 12,^X5ElO.It5SX5FlO.4) 50 CONTINUE IF(NEND) 71,71,370 v ' 71 IF(NN) 70,70,30 300 CALL EXIT END C PULSE HARMONIC GENERATOR Q=O. I PHI=(5•Ow3 .I4l6)/180.O DO 11 1=1,16 PRINT 100 100 FORMATdHl55X,38 Q 5IlX54v yO"•a>CUv tOK•a>CUv >"WC " a>•CO >"Ec•a>•TO y^Z ■ DO 10 J=l,70 PHIQ=PHI/Q TNl=(QwQ )w (I.0-2.71828S S wFyO"/ZZ TN2=1.O-COSF(PHI)-Qw (SINF(PHI) 19h TD1=Q*TN1+Q-Q*C0SF(PHI) TD2=SINF(PHI)-(I.0+Q*Q)*PHI TWD=(TM1+TN2)/3D1+TD2) tOKNPtPJD wtJAZ XIl=(Q*COSF(THE)-Q*Q*SIWF(THE))/(l.0+Q*Q) XI2= (SIWF (PHI-THE)-QxCOSF (PHI-THE ))/(l.: 0_QxQ ) XIO=XIlx (2.Tl828xx(-PHIQ))+SIWF(THE)+XI2 XI02=XI0xXI0 PLl=(2.0xXI02xQ )/3•I^l6 PL=-IO'. 0*(0.43^29)x (LOGF(PL1)) PHA=PHIxISO.0/3.l4l6 THA=THExISO.0/3.l4l6 PRIWT 103,Q,PHA,THA,XI0,XI02,PL 103 F0RI'4AT(IH ,3(3X,F10.4) ,2(3X,E10.4) ,3X,F10.4) PUWCH 500,PL 500 FORMAT(F10.4) PHI=PHI+5.0*3.l4l6/l80.O 10 COWTIWUE XI=I IF(I-IO)301,301,302 301 Q=O.2xXI GO TO 305 302 Q=5*Ox (2.0xx(XI-11.0)) 195 305 PHI=(5.0*3.1416)/180.0 11 CONTINUE PAUSE QN=O.I PHI=(5•0*3.l4l6)/180.0 DO 13 11=1,11 PRINT 200 200 FORMAT(1H1,5X,38 Q sIlX,4v y"""•a>•Uv y^Z . DO I4 JJ=I,7O \ X=(l,0/QN)*(3.l4l6-PHl/2.0) XX=I.0-2.71828**C-X) XXX=QN*XX*XX PLL=I.961-10.0*(0.43429)*LOGF(XXX) PHA=PHI*l80.0/3.l4l6 PRINT 201,QN5PHA,PLL 201 FORMAT(IH ,3X,F10.4,3X,F0.0.4,3X,F10.4) PUNCH 501,PLL 501 FORMAT(F10.4) PHI=PHI+5 • 0*3.1416/180/. O 14 CONTINUE XII=II QN=0.2*XII PHI=5'.0*3.l4l6/l80.0 196 13 CONTINUE CALL EXIT END C PL+PLL A"MKVG"WV y^^w"l 5TO)5PL(TO)5S (ll) READ IOO5N 100 FORMAT(13) DO 11 I=I5Il DO 11 J=I5TO READ IO5PLL(I5J) 10 FORMAT(F10.4) 11 CONTINUE DO 15 IN=I5N DO 16 JN=I5TO READ ZO5PL(JN) 20 FORMAT(FlOA) 16 CONTINUE • PRINT 300,IN . 300 FORMAT(IHl515) : AW CE "RN"CtW AWHtW "bN"•C 4 wl r ZN9 k wl q O 9 k k w"bC"RZ TO CONTINUE 197 PRINT 151, (S(IP)9IP=I',5.) 151 FORMAT(IH ,5(5X,P10.U)) 50 CONTINUE PRINT 301,IN 301 FORMAT(1H1,15) DO 60 IR=I,7O DO 80 10=6,11 S(IC)=PL(IR)+PLL(IC5IR) 80 CONTINUE _ PRINT 152,(S(IP),IP=6,11) 152 F0RMAT(1H ,6(5X,F10.U) 60 CONTINUE 15 CONTINUE CALL' EXIT END ■ LITERATURE CITED [1] Butter, Jr., T. W., and Aupperle, E. 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