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dc.contributor.advisorChairperson, Graduate Committee: Brock LaMeresen
dc.contributor.authorGahl, Trevor Jamesen
dc.date.accessioned2019-08-30T19:53:40Z
dc.date.available2019-08-30T19:53:40Z
dc.date.issued2019en
dc.identifier.urihttps://scholarworks.montana.edu/xmlui/handle/1/15537
dc.description.abstractToday's cyber landscape is as dangerous as ever, stemming from an ever increasing number of cybersecurity threats. A component of this danger comes from the execution of code-injection attacks that are hard to combat due to the monoculture environment fostered in today's society. One solution presented in the past, instruction set randomization, shows promise but requires large overhead both in timing and physical device space. To address this issue, a new processor architecture was developed to move instruction set randomization from software implementations to hardware. This new architecture consists of three functionally identical soft- core processors operating in parallel while utilizing individually generated random instruction sets. Successful hardware implementation and testing, using field programmable gate arrays, demonstrates the viability of the new architecture in small scale systems while also showing potential for expansion to larger systems.en
dc.language.isoenen
dc.publisherMontana State University - Bozeman, College of Engineeringen
dc.subject.lcshComputers.en
dc.subject.lcshSecurity systems.en
dc.subject.lcshElectronic data processing.en
dc.subject.lcshField programmable gate arrays.en
dc.titleTriplicated instruction set randomization in parallel heterogenous soft-core processorsen
dc.typeThesisen
dc.rights.holderCopyright 2019 by Trevor James Gahlen
thesis.degree.committeemembersMembers, Graduate Committee: Brock LaMeres (chairperson); Ross K. Snider; Brad Whitaker.en
thesis.degree.departmentElectrical & Computer Engineering.en
thesis.degree.genreThesisen
thesis.degree.nameMSen
thesis.format.extentfirstpage1en
thesis.format.extentlastpage96en
mus.data.thumbpage71en


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