Show simple item record

dc.contributor.authorMitra, Sanjay Nirendraen
dc.date.accessioned2015-05-12T20:34:24Z
dc.date.available2015-05-12T20:34:24Z
dc.date.issued1991en
dc.identifier.urihttps://scholarworks.montana.edu/xmlui/handle/1/7141en
dc.language.isoenen
dc.publisherMontana State University - Bozeman, College of Engineeringen
dc.subject.lcshIntegrated circuits--Very large scale integrationen
dc.titleVLSI implementation of a high speed systolic finite field constant multiplieren
dc.typeThesisen
dc.rights.holderCopyright 1991 by Sanjay Nirendra Mitraen
thesis.catalog.ckey60194en
thesis.degree.departmentElectrical & Computer Engineering.en
thesis.degree.genreThesisen
thesis.degree.nameMSen
thesis.format.extentfirstpage1en
thesis.format.extentlastpage217en


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record


MSU uses DSpace software, copyright © 2002-2017  Duraspace. For library collections that are not accessible, we are committed to providing reasonable accommodations and timely access to users with disabilities. For assistance, please submit an accessibility request for library material.