Theses and Dissertations at Montana State University (MSU)
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Item Implementing the Macgregor point neuron model in a Virtex-II FPGA architecture(Montana State University - Bozeman, College of Engineering, 2003) Lukes, Anthony JamesItem Continuous real-time recovery of optical spectral features distorted by fast-chirped readout(Montana State University - Bozeman, College of Engineering, 2006) Bekker, Scott Henry; Chairperson, Graduate Committee: Ross K. SniderOptical signal processors can analyze the spectra of RF signals with bandwidths of hundreds of gigahertz and achieve spectral resolutions of tens of kilohertz, far exceeding the capabilities of conventional analyzers. Modulating a broadband RF signal onto a laser beam and exposing an optical memory material to the modulated light stores the power spectrum of the input signal in the material temporarily. The power spectrum contained within the material is then extracted by measuring the intensity of the light exiting the material while exposing it to a linear frequency chirped laser spanning the bandwidth of the input signal. The major benefit of this technique is that the readout bandwidth is much lower than the bandwidth of the input signal allowing conventional photodetectors and analog to digital converters to capture the readout. A problem arises when reading out a large bandwidth in the time the signals power spectrum remains in the material. This requires a fast chirp rate, but as the chirp rate increases, so does the distortion to the readout signal. A recently developed postprocessing technique removes this distortion, allowing one to obtain high-resolution spectral information with extremely fast chirp rates. The focus of this work is the development of a practical post-processing system capable of removing the readout distortion continuously and in real-time. The original spectral recovery algorithm requires the entire readout sequence prior to processing, thus making it unsuitable for continuous real-time recovery. Therefore, the algorithm was modified to use only part of the readout signal allowing recovery during readout. Although the new algorithm exploits the computational efficiency of a fast Fourier transform, real-time recovery processing presents a computational load exceeding the capabilities of conventional programmable digital signal processors. For this reason, a field programmable gate array (FPGA) was used to meet the processing requirements by means of its parallel processing capability. The FPGA based post-processor recovers spectral features as narrow as 28 kHz read out with a chirp rate of 1 MHz/us while maintaining a processing latency less than 310 us. This work provides, for the first time, continuous real-time spectral feature recovery.Item Digital implementation of direction-of-arrival estimation techniques for smart antenna systems(Montana State University - Bozeman, College of Engineering, 2010) Abusultan, Monther Younis; Chairperson, Graduate Committee: Brock LaMeresAdaptive antenna arrays use multiple antenna elements to form directional patterns in order to improve the performance of wireless communication systems. The antenna arrays also have the ability to detect the direction of incoming signals. These two capabilities allow a smart antenna system to adaptively beamform to more efficiently communicate between nodes. The direction-of-arrival estimation is a crucial component of the smart antenna system that uses open-loop adaptive approach. Historically this estimation has been accomplished using a personal computer. Implementing the estimation in the digital domain has the potential to provide a low cost and light weight solution due to recent advances in digital integrated circuit fabrication processes. Furthermore, digital circuitry allows for more sophisticated estimation algorithms to be implemented using the computational power of modern digital devices. This thesis presents the design and prototyping of direction-of-arrival (DOA) estimation for a smart antenna system implemented on a reconfigurable digital hardware fabric. Two DOA estimation algorithms are implemented and the performance tradeoffs between a custom hardware approach and a microprocessor-based system are compared. The algorithms were implemented for a 5.8 GHz, 8-element circular antenna array and their functionality was verified using a testbed platform. The implementation and analysis presented in this work will aid system designers to understand the tradeoffs between implementing algorithms in custom hardware versus an embedded system and when a hybrid approach is more advantageous.