Triplicated instruction set randomization in parallel heterogenous soft-core processors

Abstract

Today's cyber landscape is as dangerous as ever, stemming from an ever increasing number of cybersecurity threats. A component of this danger comes from the execution of code-injection attacks that are hard to combat due to the monoculture environment fostered in today's society. One solution presented in the past, instruction set randomization, shows promise but requires large overhead both in timing and physical device space. To address this issue, a new processor architecture was developed to move instruction set randomization from software implementations to hardware. This new architecture consists of three functionally identical soft- core processors operating in parallel while utilizing individually generated random instruction sets. Successful hardware implementation and testing, using field programmable gate arrays, demonstrates the viability of the new architecture in small scale systems while also showing potential for expansion to larger systems.