Process voltage temperature compensated on-chip CMOS active inductors for Wilkinson power dividing applications

Abstract

Few academic or industry feasibility studies have been published on the implementation of Active Inductors in a standard CMOS IC process as an alternative to the physically large and typically quite lossy spiral inductors. Development efforts at the simulation level have achieved only limited success in creating an Active Inductor topology that exhibits the quality and inductive tolerance necessary for the large-scale, high-volume production common to most IC components. This thesis focuses on manufacturing and characterizing the basic component circuitry necessary for the implementation of a lumped-element Wilkinson power divider using active inductors and develops a compensation scheme to control the parameters of merit in the active inductor across a useful process, voltage and temperature operating window. Hardware results presented reinforce the need to actively compensate the Active Inductor structure implemented in a 0.6um (AMIS C5) CMOS process. Simulation results presented show the benefits of a compensated Active Inductor incorporated into a typical RF network.