Theses and Dissertations at Montana State University (MSU)
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Item Novel approach to fault tolerance in space computers leveraging the RISC-V architecture(Montana State University - Bozeman, College of Engineering, 2023) Major, Chris Michel; Chairperson, Graduate Committee: Brad WhitakerAs the aerospace industry continues to accelerate in growth and mission frequency, the demand for high-performance computers that can withstand radiation environments has become a critical need within the field. Traditional space computing systems rely on specialized and complex means of radiation resistance, but more modern systems seek to implement redundant components to mitigate radiation effects. This dissertation presents a novel approach to radiation-tolerant space computing, based on Montana State University's RadPC program, by developing a resilient architecture leveraging the open-source RISC- V processor. The architecture discussed is designed to withstand radiation environments and engage repairs for damaged sections using commercial, off-the-shelf components - without requiring radiation-hardened fabrication processes or specialized manufacturing. This dissertation discusses the design and performance of the components required to ensure radiation resilience in the system, reconfigure compromised processors in the event of damage, and provides a characterization of the system's overall performance in various space environments.Item Fault injection system for FPGA-based space computers(Montana State University - Bozeman, College of Engineering, 2023) Austin, Hezekiah Ajax; Chairperson, Graduate Committee: Brock LaMeresAbstract: Simulation of radiation effects in aerospace computers is a key testing and verification component to space operations. Contemporary computer architectures utilizing Field Programmable Gate Arrays (FPGA) requires particular focus in testing the configuration memory of the device for faults that cannot be recovered using traditional strategies. Faults in the configuration memory propagate to the hardware settings of the FPGA, changing the implemented logic circuit functionality. The effects of faults in the configuration memory are unpredictable, limiting the effectiveness of computer simulation and analysis. Therefore, designers of FPGA-based aerospace computers prefer to physically induce faults in the configuration memory to measure their impact. This allows the results of configuration memory fault injection used to classify faults occurring during space operation. The process is difficult to implement as the FPGA configuration memory is large, often undocumented, and the injection process is tedious when done manually. This paper presents the results of the deployment of two FPGA-based aerospace computers payloads to the International Space Station and the subsequently developed process for configuration memory fault injection. The injections are designed to simulate errors caused by radiation strikes to the computer hardware. These injections were performed on duplicate hardware to the RadPC payloads that operated on the ISS and was bombardment by real radiation. This provided the ability to see if the ground-based injection was correlated to real flight data. The developed process is able to inject single bit faults, which represents the majority of faults observed in configuration memory for space applications, and continuous injection, which stress tests the aerospace computer's recovery capability. Depending on the effects of the injected fault, the error is marked as either repairable, nonrepairable and propagating, or nonrepairable and nonpropagating. The result of this testing illustrates the key components in the implemented computer architecture which are vulnerable to faults in the configuration memory. Vulnerable components include the softcores, voter components, and the input logic. The process allows these key components to be isolated for further testing and the comparison of payload results to configuration memory testing on the ground.Item RadPC@Scale: an approach to mitigate single event upsets in the memory of space computers(Montana State University - Bozeman, College of Engineering, 2022) Williams, Justin Patrick; Chairperson, Graduate Committee: Brock LaMeresThis thesis presents the flight test results of a single event upset (SEU) mitigation strategy for computer data memory. This memory fault mitigation strategy is part of a larger effort to build a radiation tolerant computing system using commercial-off-the-shelf (COTS) field programmable gate arrays (FPGAs) called RadPC. While previous iterations of RadPC used FPGA block RAM (BRAM) for its data memory, the specific component of RadPC that is presented in this paper is a novel external memory scheme with accompanying systems that can detect, and correct faults that occur in the proposed data memory of the computer while allowing the computer to continue foreground operation. A prototype implementation of this memory protection scheme was flown on a Raven Aerostar Thunderhead high-altitude balloon system in July of 2021. This flight carried the experiment to an altitude of 75,000 feet for 50 hours allowing the memory in the experiment to be bombarded with ionizing radiation without being attenuated by the majority of Earth's atmosphere. This thesis discusses the details of the fault mitigation strategy, the design-of-experiments for the flight demonstration, and the results from the flight data. This thesis may be of interest to engineers that are designing flight computer systems that will be exposed to ionizing radiation and are looking for a lower cost SEU mitigation strategy compared to existing radiation- hardened solutions.Item A fault-tolerant computer architecture for space vehicle applications(Montana State University - Bozeman, College of Engineering, 2012) Hane, Jennifer Susan; Chairperson, Graduate Committee: Brock LaMeresThe discovery of new methods to protect electronics from harsh radiation environments outside earth's atmosphere is important to the future of space exploration. Reconfigurable, SRAM-based Field Programmable Gate Arrays (FPGAs) are especially promising candidates for future spacecraft computing platforms; however, their susceptibility to radiation-induced faults in their configuration memory makes their use a challenge. This thesis presents the design and testing of a redundant fault-tolerant architecture targeted at the Xilinx Virtex-6 FPGA. The architecture is based on a combination of triple modulo redundancy (TMR), numerous spare units, repair (scrubbing), and environmental awareness. By using the spares and the partial reconfiguration capabilities of the FPGA, the system can remain operational while repair of damaged modules proceeds in the background. The environmental awareness is supplied by a multi-pixel radiation sensor designed to rest above the FPGA chip, providing information about which areas of the chip have received radiation strikes. The system places these potentially damaged areas first in the queue for scrubbing. Four implementations of the architecture with different types of computing module and numbers of spares reveal its versatility and scalability. These four demonstration systems were modeled with theoretical Markov calculations, for the purpose of determining their reliability. They were also implemented on Xilinx hardware and tested by the injection of simulated faults, based on realistic orbital fault rate data from the Cosmic Ray Effects on Micro-Electronics Code (CREME96) tool. These results confirm that the systems will be highly reliable under typical earth orbit conditions. The results also demonstrate that the inclusion of numerous spares and the sensor both lead to substantial improvements in the Mean Time Before Failure, over a traditional TMR system with only three modules and scrubbing.