Theses and Dissertations at Montana State University (MSU)

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Injection attack immunity using redundant heterogeneous processing cores
(Montana State University - Bozeman, College of Engineering, 2023) Barney, Colter Ross; Chairperson, Graduate Committee: Brock LaMeres
Technology is an integral part of modern society. Devices such as smart lights, locks and appliances are becoming more commonplace. This class of devices are called embedded systems. Embedded systems can be targeted by malicious cyber attacks just as a normal computer can. Unfortunately, many techniques used to secure and protect normal computers do not work on embedded systems. New security techniques must be developed and designed to protect embedded systems. This paper investigates using physically diverse processing cores to defeat cyber attacks in real time. Diverse processing cores were implemented using reconfigurable hardware devices called FPGAs. The use of FPGAs allows diverse cores to be utilized, without losing the benefits gained from standardized processors. The cores implemented were based on a commercial processor made by Texas Instruments (TI). Modeling the diverse cores after a commercial processor enables the cores to utilize development tools created for TI's processor. A complete system was built using diverse processors to prove the feasibility and usability of secure embedded systems. The cores were used to control a realistic embedded system application. While operating, the cores were subjected to a cyber attack, and they were able to nullify the attack. An identical setup was created using the commercially available processor. Attacking the commercial processor compromised the application and reinforced the need for secure systems. The techniques investigated and utilized in this paper can be expanded to increase security in the many embedded systems that have become an essential part of modern lifestyles.
Fault injection system for FPGA-based space computers
(Montana State University - Bozeman, College of Engineering, 2023) Austin, Hezekiah Ajax; Chairperson, Graduate Committee: Brock LaMeres
Abstract: Simulation of radiation effects in aerospace computers is a key testing and verification component to space operations. Contemporary computer architectures utilizing Field Programmable Gate Arrays (FPGA) requires particular focus in testing the configuration memory of the device for faults that cannot be recovered using traditional strategies. Faults in the configuration memory propagate to the hardware settings of the FPGA, changing the implemented logic circuit functionality. The effects of faults in the configuration memory are unpredictable, limiting the effectiveness of computer simulation and analysis. Therefore, designers of FPGA-based aerospace computers prefer to physically induce faults in the configuration memory to measure their impact. This allows the results of configuration memory fault injection used to classify faults occurring during space operation. The process is difficult to implement as the FPGA configuration memory is large, often undocumented, and the injection process is tedious when done manually. This paper presents the results of the deployment of two FPGA-based aerospace computers payloads to the International Space Station and the subsequently developed process for configuration memory fault injection. The injections are designed to simulate errors caused by radiation strikes to the computer hardware. These injections were performed on duplicate hardware to the RadPC payloads that operated on the ISS and was bombardment by real radiation. This provided the ability to see if the ground-based injection was correlated to real flight data. The developed process is able to inject single bit faults, which represents the majority of faults observed in configuration memory for space applications, and continuous injection, which stress tests the aerospace computer's recovery capability. Depending on the effects of the injected fault, the error is marked as either repairable, nonrepairable and propagating, or nonrepairable and nonpropagating. The result of this testing illustrates the key components in the implemented computer architecture which are vulnerable to faults in the configuration memory. Vulnerable components include the softcores, voter components, and the input logic. The process allows these key components to be isolated for further testing and the comparison of payload results to configuration memory testing on the ground.
RadPC@Scale: an approach to mitigate single event upsets in the memory of space computers
(Montana State University - Bozeman, College of Engineering, 2022) Williams, Justin Patrick; Chairperson, Graduate Committee: Brock LaMeres
This thesis presents the flight test results of a single event upset (SEU) mitigation strategy for computer data memory. This memory fault mitigation strategy is part of a larger effort to build a radiation tolerant computing system using commercial-off-the-shelf (COTS) field programmable gate arrays (FPGAs) called RadPC. While previous iterations of RadPC used FPGA block RAM (BRAM) for its data memory, the specific component of RadPC that is presented in this paper is a novel external memory scheme with accompanying systems that can detect, and correct faults that occur in the proposed data memory of the computer while allowing the computer to continue foreground operation. A prototype implementation of this memory protection scheme was flown on a Raven Aerostar Thunderhead high-altitude balloon system in July of 2021. This flight carried the experiment to an altitude of 75,000 feet for 50 hours allowing the memory in the experiment to be bombarded with ionizing radiation without being attenuated by the majority of Earth's atmosphere. This thesis discusses the details of the fault mitigation strategy, the design-of-experiments for the flight demonstration, and the results from the flight data. This thesis may be of interest to engineers that are designing flight computer systems that will be exposed to ionizing radiation and are looking for a lower cost SEU mitigation strategy compared to existing radiation- hardened solutions.
Enabling rapid prototyping of audio signal processing systems using system-on-chip field programmable gate arrays
(Montana State University - Bozeman, College of Engineering, 2020) Vannoy, Trevor Charles; Chairperson, Graduate Committee: Ross K. Snider
System-on-Chip Field Programmable Gate Arrays are excellent devices for high performance, low latency signal processing. Unfortunately, they are notoriously difficult to use, requiring significant hardware and software engineering expertise. To address these challenges, a development framework is created that utilizes graphical programming and automatic code generation; this framework reduces development time and reduces the need to be an expert in Field Programmable Gate Arrays. A sound effects processor and a real-time audio beamformer were created to showcase the development framework and serve as reference designs for other developers. The development framework, coupled with open source audio hardware, enables both experts and non-experts to rapidly prototype audio signal processing systems using System-on-Chip Field Programmable Gate Arrays.
Optimization of error correcting codes in FPGA fabric onboard cube satellites
(Montana State University - Bozeman, College of Engineering, 2019) Tamke, Skylar Anthony; Chairperson, Graduate Committee: Brock LaMeres
The harmful effects of radiation on electronics in space is a difficult problem for the aerospace industry. Radiation can cause faults in electronics systems like memory corruption or logic flips. One possible solution to combat these effects is to use FPGAs with radiation mitigation techniques. The following Masters of Science thesis details the design and testing of a radiation tolerant computing system at MSU. The computer is implemented on a field programmable gate array (FPGA), the reconfigurable nature of FPGAs allows for novel fault mitigation techniques on commercial devices. Some common fault mitigation techniques involve triple modular redundancy, memory scrubbing, and error correction codes which when paired with the partial reconfiguration. Our radiation tolerant computer has been in development for over a decade at MSU and is continuously being developed to expand its radiation mitigation techniques. This thesis will discuss the benefits of adding error correcting codes to the ever developing radiation tolerant computing system. Error correcting codes have been around since the late 1940's when Richard Hamming decided that the Bell computers he did his work on could automate their own error correcting capabilities. Since then a variety of error correcting codes have been developed for use in different situations. This thesis will cover several popular error correcting method for RF communication and look at using them in memory in our radiation tolerant computing system.
Real-time software-defined free-space optical communication system
(Montana State University - Bozeman, College of Engineering, 2019) Sultana, Nishat; Chairperson, Graduate Committee: Ioannis Roudas
Next-generation software-defined free-space optical (FSO) communication systems may substitute many conventional radio communication systems. The conventional single-purpose dedicated hardware resources in the telecommunication systems have significant limitations since they provide a single communication service using a specific standard at a time. It is also expensive to upgrade to the emerging new standards such as 5G New Radio (5GNR) by substituting the existing hardware resources. Reprogrammable FPGA-based Software Defined Radio (SDR) technology is deployed as a feasible solution to this problem since they can be reconfigured simultaneously realizing the user requirements. When integrated with the FSO system it opens a plethora of opportunities since the Visible Light Frequency Spectrum is barely occupied by the existing technologies and can be designed cost-effectively for the vast bandwidth it has to offer. In this thesis work, we implemented a real-time FSO communication system using an SDR platform. A fully-functional optical communication link has been accomplished using the Universal Software Radio Peripheral (USRP), MATLAB-Simulink communication toolbox and hardware support package, Laser diode, and a Photodetector. We demonstrate successful transmission and reception of baseband signals with very low bit error rate. Visually identical transmitted and received signals also validate the accuracy of the simulation results when compared to those obtained from the real-time FSO-SDR communication system.
Triplicated instruction set randomization in parallel heterogenous soft-core processors
(Montana State University - Bozeman, College of Engineering, 2019) Gahl, Trevor James; Chairperson, Graduate Committee: Brock LaMeres
Today's cyber landscape is as dangerous as ever, stemming from an ever increasing number of cybersecurity threats. A component of this danger comes from the execution of code-injection attacks that are hard to combat due to the monoculture environment fostered in today's society. One solution presented in the past, instruction set randomization, shows promise but requires large overhead both in timing and physical device space. To address this issue, a new processor architecture was developed to move instruction set randomization from software implementations to hardware. This new architecture consists of three functionally identical soft- core processors operating in parallel while utilizing individually generated random instruction sets. Successful hardware implementation and testing, using field programmable gate arrays, demonstrates the viability of the new architecture in small scale systems while also showing potential for expansion to larger systems.
Development of a smart camera system using a system on module FPGA
(Montana State University - Bozeman, College of Engineering, 2017) Dack, Connor Aquila; Chairperson, Graduate Committee: Ross K. Snider
Imaging systems can now produce more data than conventional PCs with frame grabbers can process in real-time. Moving real-time custom computation as close as possible to the image sensor will alleviate the bandwidth bottle-neck of moving data multiple times through buffers in conventional PC systems, which are also computation bottlenecks. An example of a high bandwidth, high computation application is the use of hyperspectral imagers for sorting applications. Hyperspectral imagers capture hundreds of colors ranging from the visible spectrum to the infrared. This masters thesis continues the development of the hyperspectral smart camera by integrating the image sensor with a field programmable gate array (FPGA) and by developing an object tracking algorithm for use during the sorting process, with the goal of creating a single compact embedded solution. An FPGA is a hardware programmable integrated circuit that can be reprogrammed depending on the application. The prototype integration involves the development of a custom printed circuit board to connect the data and control lines between the sensor, the FPGA, and the control code to read data from the sensor. The hyperspectral data is processed on the FPGA and is combined with the object edges to make a decision on the quality of the object. The object edges are determined using a line scan camera, which provides data via the Camera Link interface, and a custom object tracking algorithm. The object tracking algorithm determines the horizontal edges and center of the object while also tracking the vertical edges and center of the object. The object information is then passed to the air jet sorting subsystem which ejects bad objects. The solution is to integrate the hyperspectral image sensor, the two processing algorithms, and Camera Link interface into a single, compact unit by implementing the design on the Intel Arria 10 System on Module with custom printed circuit boards.
A radiation tolerant computer mission to the International Space Station
(Montana State University - Bozeman, College of Engineering, 2017) Julien, Connor Russell; Chairperson, Graduate Committee: Brock LaMeres
The harmful effects of radiation on electronics used in space poses a difficult problem for the aerospace industry. Memory corruption and other faults caused by the harsh radiation environment are difficult to mitigate. The following Masters of Science thesis describes the design and testing of a radiation tolerant, low-cost computer system to meet the increasing demand of fault tolerant space computing. The computer is implemented on a modern Field Programmable Gate Array (FPGA), which enables a novel fault mitigation strategy to be deployed on a commercial part, thus reducing the cost of the system. Using modern processing nodes as small as 28nm, FPGAs can provide increased computational performance and power efficiency. Common mitigation techniques like triple modular redundancy and memory scrubbing are expanded by utilizing partial reconfiguration on the FPGA and by introducing extra spare processors. Our computer system has been in development at Montana State University for the past 10 years and has undergone a series of technology demonstrations to increase its technical readiness level. These include high energy particle bombardment at the Texas A&M Radiation Effects Facility, 8 high altitude balloon flights to 30km, and two sounding rocket flights to altitudes greater than 120km. This computer is currently being demonstrated onboard the International Space Station and will be the payload for two stand-alone small satellite missions in low Earth orbit in 2018. This Masters of Science thesis presents improvements to the system by moving the design to a new, low power FPGA with a new processor synchronization method. This thesis will present the design, testing, and characterization of the computer system along with conveying data collected by the experiment on the International Space Station.
A system to eavesdrop on marmosets
(Montana State University - Bozeman, College of Engineering, 2015) Casebeer, Christopher Ness; Chairperson, Graduate Committee: Ross K. Snider
This masters thesis describes developing a custom digital recording system to record the vocalizations and behavior of marmosets, which are small primates native to the northeast of Brazil. Animal behavior scientists have traditionally studied communications between only a 'sender' and a 'receiver'. Animal communications however are hypothesized to occur in communication networks involving more than just a pair of animals. In this project a miniaturized recording system aimed at acquiring data to study the communication networks of the common marmoset is underway. The acoustic recording collar project aims to develop a wearable recording embedded platform for a freely behaving primate. A custom embedded platform utilizing a field programmable gate array (FPGA) has been developed to prototype the system. A hardware description language (HDL) has been used to create the FPGA architecture for the collar application, which in this case is the VHSIC Hardware Description Language (VHDL). Sensors used and developed for this application include a global positioning system (GPS), inertial measurement unit (IMU), and digital MEMS microphone. These sensors provide position and accurate time information, behaviorally related motion information, and the acoustic environment of the marmoset. This data comprises the Behavioral Acoustic Biome of the marmoset. Storage of the behavioral acoustic biome data occurs on a local microSD ash memory card. A printed circuit board of footprint 1.36 by 1.18 inches has been completed and the system will be soon fitted to a 3D printed collar wearable by the marmoset. Demonstration of sensor data logging to the microSD ash has been completed. Other developments of the embedded system are ongoing. Ultimately, fitting multiple wearable devices across a troop of freely behaving marmosets will allow novel studies of communication networks in the common marmoset to be undertaken.

Theses and Dissertations at Montana State University (MSU)

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