VLSI implementation of a high speed systolic finite field constant multiplier
| dc.contributor.author | Mitra, Sanjay Nirendra | en |
| dc.date.accessioned | 2015-05-12T20:34:24Z | |
| dc.date.available | 2015-05-12T20:34:24Z | |
| dc.date.issued | 1991 | en |
| dc.identifier.uri | https://scholarworks.montana.edu/handle/1/7141 | en |
| dc.language.iso | en | en |
| dc.publisher | Montana State University - Bozeman, College of Engineering | en |
| dc.rights.holder | Copyright 1991 by Sanjay Nirendra Mitra | en |
| dc.subject.lcsh | Integrated circuits--Very large scale integration | en |
| dc.title | VLSI implementation of a high speed systolic finite field constant multiplier | en |
| dc.type | Thesis | en |
| thesis.catalog.ckey | 60194 | en |
| thesis.degree.department | Electrical & Computer Engineering. | en |
| thesis.degree.genre | Thesis | en |
| thesis.degree.name | MS | en |
| thesis.format.extentfirstpage | 1 | en |
| thesis.format.extentlastpage | 217 | en |
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