A radiation tolerant computer mission to the International Space Station

Abstract

The harmful effects of radiation on electronics used in space poses a difficult problem for the aerospace industry. Memory corruption and other faults caused by the harsh radiation environment are difficult to mitigate. The following Masters of Science thesis describes the design and testing of a radiation tolerant, low-cost computer system to meet the increasing demand of fault tolerant space computing. The computer is implemented on a modern Field Programmable Gate Array (FPGA), which enables a novel fault mitigation strategy to be deployed on a commercial part, thus reducing the cost of the system. Using modern processing nodes as small as 28nm, FPGAs can provide increased computational performance and power efficiency. Common mitigation techniques like triple modular redundancy and memory scrubbing are expanded by utilizing partial reconfiguration on the FPGA and by introducing extra spare processors. Our computer system has been in development at Montana State University for the past 10 years and has undergone a series of technology demonstrations to increase its technical readiness level. These include high energy particle bombardment at the Texas A&M Radiation Effects Facility, 8 high altitude balloon flights to 30km, and two sounding rocket flights to altitudes greater than 120km. This computer is currently being demonstrated onboard the International Space Station and will be the payload for two stand-alone small satellite missions in low Earth orbit in 2018. This Masters of Science thesis presents improvements to the system by moving the design to a new, low power FPGA with a new processor synchronization method. This thesis will present the design, testing, and characterization of the computer system along with conveying data collected by the experiment on the International Space Station.