Optimization of error correcting codes in FPGA fabric onboard cube satellites

Abstract

The harmful effects of radiation on electronics in space is a difficult problem for the aerospace industry. Radiation can cause faults in electronics systems like memory corruption or logic flips. One possible solution to combat these effects is to use FPGAs with radiation mitigation techniques. The following Masters of Science thesis details the design and testing of a radiation tolerant computing system at MSU. The computer is implemented on a field programmable gate array (FPGA), the reconfigurable nature of FPGAs allows for novel fault mitigation techniques on commercial devices. Some common fault mitigation techniques involve triple modular redundancy, memory scrubbing, and error correction codes which when paired with the partial reconfiguration. Our radiation tolerant computer has been in development for over a decade at MSU and is continuously being developed to expand its radiation mitigation techniques. This thesis will discuss the benefits of adding error correcting codes to the ever developing radiation tolerant computing system. Error correcting codes have been around since the late 1940's when Richard Hamming decided that the Bell computers he did his work on could automate their own error correcting capabilities. Since then a variety of error correcting codes have been developed for use in different situations. This thesis will cover several popular error correcting method for RF communication and look at using them in memory in our radiation tolerant computing system.